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    <title>topic Data linear address does not appear with PEBS sampling in some architectures in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Data-linear-address-does-not-appear-with-PEBS-sampling-in-some/m-p/1092155#M5674</link>
    <description>&lt;P&gt;Hi all,&lt;/P&gt;

&lt;P&gt;currently I'm trying to enable PEBS module for application profiling&lt;/P&gt;

&lt;P&gt;by using&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;simple PEBS example in pmu-tool&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;(&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&lt;A href="https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/519908)" target="_blank"&gt;https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/519908)&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;For further checking, I simply added codes that dump IP and data linear address (0x98H) of PEBS record,&lt;/P&gt;

&lt;P&gt;but, in some platforms (SandyBridge and IvyBridge based platform), data linear address field is always nil, while IPs are dumped in normal.&lt;/P&gt;

&lt;P&gt;I checked the same example in SkyLake based platform, IP and data linear address appear in normal.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Is there any limitation for extracting data linear address in SandyBridge or IvyBridge platforms?&lt;/P&gt;

&lt;P&gt;I checked Intel SDM, but it says data linear address field is enhanced for further profiling after SandyBridge architecture.&lt;/P&gt;

&lt;P&gt;If anyone knows about this, please give me some advices.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;FYI, here are platform specifications that I tried:&lt;/P&gt;

&lt;P&gt;1. Intel i5-2500 (Sandybridge, PEBS v1) - IP(08H): O, DLA (98H): nil&lt;/P&gt;

&lt;P&gt;2. Intel Xeon E5-2640 v2 (IvyBridge, PEBS v1) - IP (08H): O, DLA (98H): nil&lt;/P&gt;

&lt;P&gt;3. Intel i7-6700K (SkyLake, PEBS v3) - IP (08H): O, DLA (98H): O&lt;/P&gt;

&lt;P&gt;and I checked for 'MEM_LOAD_UOPS_RETIRED.L3_MISS (D1H_20H)' &amp;nbsp;and 'UOPS_RETIRED.ALL (C2H_01H)' events.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Jaeyoung Jang&lt;/P&gt;</description>
    <pubDate>Fri, 10 Jun 2016 07:18:37 GMT</pubDate>
    <dc:creator>jang__jaeyoung</dc:creator>
    <dc:date>2016-06-10T07:18:37Z</dc:date>
    <item>
      <title>Data linear address does not appear with PEBS sampling in some architectures</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Data-linear-address-does-not-appear-with-PEBS-sampling-in-some/m-p/1092155#M5674</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;

&lt;P&gt;currently I'm trying to enable PEBS module for application profiling&lt;/P&gt;

&lt;P&gt;by using&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;simple PEBS example in pmu-tool&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;(&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;&lt;A href="https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/519908)" target="_blank"&gt;https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/519908)&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;For further checking, I simply added codes that dump IP and data linear address (0x98H) of PEBS record,&lt;/P&gt;

&lt;P&gt;but, in some platforms (SandyBridge and IvyBridge based platform), data linear address field is always nil, while IPs are dumped in normal.&lt;/P&gt;

&lt;P&gt;I checked the same example in SkyLake based platform, IP and data linear address appear in normal.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Is there any limitation for extracting data linear address in SandyBridge or IvyBridge platforms?&lt;/P&gt;

&lt;P&gt;I checked Intel SDM, but it says data linear address field is enhanced for further profiling after SandyBridge architecture.&lt;/P&gt;

&lt;P&gt;If anyone knows about this, please give me some advices.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;FYI, here are platform specifications that I tried:&lt;/P&gt;

&lt;P&gt;1. Intel i5-2500 (Sandybridge, PEBS v1) - IP(08H): O, DLA (98H): nil&lt;/P&gt;

&lt;P&gt;2. Intel Xeon E5-2640 v2 (IvyBridge, PEBS v1) - IP (08H): O, DLA (98H): nil&lt;/P&gt;

&lt;P&gt;3. Intel i7-6700K (SkyLake, PEBS v3) - IP (08H): O, DLA (98H): O&lt;/P&gt;

&lt;P&gt;and I checked for 'MEM_LOAD_UOPS_RETIRED.L3_MISS (D1H_20H)' &amp;nbsp;and 'UOPS_RETIRED.ALL (C2H_01H)' events.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thanks,&lt;/P&gt;

&lt;P&gt;Jaeyoung Jang&lt;/P&gt;</description>
      <pubDate>Fri, 10 Jun 2016 07:18:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Data-linear-address-does-not-appear-with-PEBS-sampling-in-some/m-p/1092155#M5674</guid>
      <dc:creator>jang__jaeyoung</dc:creator>
      <dc:date>2016-06-10T07:18:37Z</dc:date>
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