https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098983#M5803 <P>The invariant TSC should only change frequency if the 100 MHz reference clock changes frequency.&nbsp; Since this is generated outside the processor, the processor temperature should not have a direct impact.&nbsp; (There will be an indirect impact if the processor heats up the entire motherboard, of course.)</P> <P>The amount of temperature-induced drift of this reference clock will depend on the quality of the implementation.&nbsp;&nbsp;&nbsp; For a clock that is going to be used for the PCIe interface, the PCIe standard specifies that the clock must be accurate to within 300ppm, so the worst case allowable would be +/- 0.03%.</P> <P>If I am reading the datasheets correctly, clock generators for Intel processors are typically specified to have an accuracy of no worse than 100 ppm, or +/- 0.01%.</P> Mon, 28 Nov 2016 21:25:40 GMT McCalpinJohn 2016-11-28T21:25:40Z https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098982#M5802 Given an invariant TSC on a relatively recent (Ivy Bridge+) chip, to what extent is the frequency the TSC is incremented at influenced by temperature? Does anyone have any measurements of this? Mon, 28 Nov 2016 19:14:50 GMT https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098982#M5802 Corey_R_ 2016-11-28T19:14:50Z https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098983#M5803 <P>The invariant TSC should only change frequency if the 100 MHz reference clock changes frequency.&nbsp; Since this is generated outside the processor, the processor temperature should not have a direct impact.&nbsp; (There will be an indirect impact if the processor heats up the entire motherboard, of course.)</P> <P>The amount of temperature-induced drift of this reference clock will depend on the quality of the implementation.&nbsp;&nbsp;&nbsp; For a clock that is going to be used for the PCIe interface, the PCIe standard specifies that the clock must be accurate to within 300ppm, so the worst case allowable would be +/- 0.03%.</P> <P>If I am reading the datasheets correctly, clock generators for Intel processors are typically specified to have an accuracy of no worse than 100 ppm, or +/- 0.01%.</P> Mon, 28 Nov 2016 21:25:40 GMT https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098983#M5803 McCalpinJohn 2016-11-28T21:25:40Z https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098984#M5804 <P>Ok, thanks John!</P> Mon, 28 Nov 2016 22:26:37 GMT https://community.intel.com/t5/Software-Tuning-Performance/TSC-frequency-variations-with-temperature/m-p/1098984#M5804 Corey_R_ 2016-11-28T22:26:37Z