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    <title>topic Attributing lost cycles to cache misses and mis predictsIdentifying if data locality and branch mis predicts in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Attributing-lost-cycles-to-cache-misses-and-mis/m-p/1104287#M5917</link>
    <description>&lt;P&gt;Is there a way to identify between two code execution points, like for example start and end of a program how many cycles were impacted because of cache misses and branch mispredicts.&lt;/P&gt;

&lt;P&gt;I want to understand if the number is meaningful for my application. My application finishes a performance sensitive task in 100ms and I want to know if the total impact of missed caches and mispredicts even comes to let's say 10ms.&lt;/P&gt;</description>
    <pubDate>Tue, 21 Jun 2016 18:26:10 GMT</pubDate>
    <dc:creator>Hayden_L_</dc:creator>
    <dc:date>2016-06-21T18:26:10Z</dc:date>
    <item>
      <title>Attributing lost cycles to cache misses and mis predictsIdentifying if data locality and branch mis predicts</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Attributing-lost-cycles-to-cache-misses-and-mis/m-p/1104287#M5917</link>
      <description>&lt;P&gt;Is there a way to identify between two code execution points, like for example start and end of a program how many cycles were impacted because of cache misses and branch mispredicts.&lt;/P&gt;

&lt;P&gt;I want to understand if the number is meaningful for my application. My application finishes a performance sensitive task in 100ms and I want to know if the total impact of missed caches and mispredicts even comes to let's say 10ms.&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jun 2016 18:26:10 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Attributing-lost-cycles-to-cache-misses-and-mis/m-p/1104287#M5917</guid>
      <dc:creator>Hayden_L_</dc:creator>
      <dc:date>2016-06-21T18:26:10Z</dc:date>
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    <item>
      <title>FYI, I know of RESOURCE_STALL</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Attributing-lost-cycles-to-cache-misses-and-mis/m-p/1104288#M5918</link>
      <description>&lt;P&gt;FYI, I know of RESOURCE_STALL.BR_MISS_CLEAR ​-- this is&amp;nbsp;a good general counter. Is there an equivalent for L1D and L2 cache misses also I couldn't find one .. maybe I have to construct one using the ones available, and any help here is appreciated.&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jun 2016 18:30:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Attributing-lost-cycles-to-cache-misses-and-mis/m-p/1104288#M5918</guid>
      <dc:creator>Hayden_L_</dc:creator>
      <dc:date>2016-06-21T18:30:55Z</dc:date>
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