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    <title>topic Cache Set in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/Cache-Set/m-p/795781#M603</link>
    <description>I have the some problem!</description>
    <pubDate>Tue, 26 Jun 2012 02:54:58 GMT</pubDate>
    <dc:creator>Wander_Gomes</dc:creator>
    <dc:date>2012-06-26T02:54:58Z</dc:date>
    <item>
      <title>Cache Set</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Cache-Set/m-p/795780#M602</link>
      <description>I'm using a E5-2690 processor, and I would like to know it there is a way to know, given an addr (from a pointer), what cache set (L1, L2 and L3) this address is mapped to. Is it just something like: addr % number_of_sets ? Does make sense do it with a pointer (virtual address)?&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;</description>
      <pubDate>Tue, 26 Jun 2012 00:19:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Cache-Set/m-p/795780#M602</guid>
      <dc:creator>Rafael_Silva</dc:creator>
      <dc:date>2012-06-26T00:19:12Z</dc:date>
    </item>
    <item>
      <title>Cache Set</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/Cache-Set/m-p/795781#M603</link>
      <description>I have the some problem!</description>
      <pubDate>Tue, 26 Jun 2012 02:54:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/Cache-Set/m-p/795781#M603</guid>
      <dc:creator>Wander_Gomes</dc:creator>
      <dc:date>2012-06-26T02:54:58Z</dc:date>
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