topic locking code and data in L1/L2 cache. in Software Tuning, Performance Optimization & Platform Monitoring https://community.intel.com/t5/Software-Tuning-Performance/locking-code-and-data-in-L1-L2-cache/m-p/1121378#M6192 <P>anyone can provide with sample code in ASM64, for locking code and data in L1/L2? I am an ARM guy transitioning to ​Intel architecture. my code will run on xeon e3-1240v3. tnx much.</P> <P>&nbsp;</P> <P>&nbsp;</P> Fri, 21 Oct 2016 02:35:31 GMT ovidiu_n_ 2016-10-21T02:35:31Z locking code and data in L1/L2 cache. https://community.intel.com/t5/Software-Tuning-Performance/locking-code-and-data-in-L1-L2-cache/m-p/1121378#M6192 <P>anyone can provide with sample code in ASM64, for locking code and data in L1/L2? I am an ARM guy transitioning to ​Intel architecture. my code will run on xeon e3-1240v3. tnx much.</P> <P>&nbsp;</P> <P>&nbsp;</P> Fri, 21 Oct 2016 02:35:31 GMT https://community.intel.com/t5/Software-Tuning-Performance/locking-code-and-data-in-L1-L2-cache/m-p/1121378#M6192 ovidiu_n_ 2016-10-21T02:35:31Z