https://community.intel.com/t5/Software-Tuning-Performance/HARP-Hardware-Accelerator-Research-Program/m-p/1126570#M6321 <P>&nbsp;Hi,</P> <P>Is it possible to monitor cache state from a HARP IP? My goal is to monitor memory address ranges and act, from the IP side, on modifications in such ranges.</P> <P>Since the FPGA has a cache coherent with its associated Xeon's LLC, and such coherence is done through QPI transactions, I am wondering if its possible to snoop on such messages and act on them.</P> <P>Thanks in advance!</P> <P>PS: I failed to find a HARP specific thread. So, If this is not the correct place to discuss HARP related topics, please direct me to them.</P> Mon, 10 Sep 2018 20:55:12 GMT Jde_C 2018-09-10T20:55:12Z https://community.intel.com/t5/Software-Tuning-Performance/HARP-Hardware-Accelerator-Research-Program/m-p/1126570#M6321 <P>&nbsp;Hi,</P> <P>Is it possible to monitor cache state from a HARP IP? My goal is to monitor memory address ranges and act, from the IP side, on modifications in such ranges.</P> <P>Since the FPGA has a cache coherent with its associated Xeon's LLC, and such coherence is done through QPI transactions, I am wondering if its possible to snoop on such messages and act on them.</P> <P>Thanks in advance!</P> <P>PS: I failed to find a HARP specific thread. So, If this is not the correct place to discuss HARP related topics, please direct me to them.</P> Mon, 10 Sep 2018 20:55:12 GMT https://community.intel.com/t5/Software-Tuning-Performance/HARP-Hardware-Accelerator-Research-Program/m-p/1126570#M6321 Jde_C 2018-09-10T20:55:12Z