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    <title>topic About PMU in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/About-PMU/m-p/1130097#M6389</link>
    <description>&lt;P&gt;I'm new to PMU development, I'm curious about the following question about PMU:&lt;/P&gt;

&lt;P&gt;1) I have read&amp;nbsp;IA32_MISC_ENABLE MSR and the bit[7] always is zero , but the bit[12] always set, what does it mean? The CPU is supported PEBS or not supported??&lt;/P&gt;

&lt;P&gt;2) Does PEBS provided the functionality that can trap all of branch , such as , syscall ? what is the basic step for doing this?&lt;/P&gt;

&lt;P&gt;3) without PEBS , I tired to set a PMC0 with&amp;nbsp;Ia32PerfEvtseL0 , and set the PMC0 to be negative number , &amp;nbsp;however, the PMI doesn't happened... why is that..??&lt;/P&gt;

&lt;P&gt;4) I have do a following setting , but there is not PMI generated&lt;/P&gt;

&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="{AA2A6F71-E766-4504-BCF3-B64F0857760A}.png"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/9714i152DBDFCB8754BE2/image-size/large?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="{AA2A6F71-E766-4504-BCF3-B64F0857760A&amp;amp;#125;.png" alt="{AA2A6F71-E766-4504-BCF3-B64F0857760A&amp;amp;#125;.png" /&gt;&lt;/span&gt;&lt;/P&gt;

&lt;P&gt;CPU Model : 60&amp;nbsp;&lt;/P&gt;

&lt;P&gt;where g_Event is 0xC2 and g_mask is 1&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thank you :)&lt;/P&gt;

&lt;DIV&gt;&lt;IMG src="C:\Users\KELVIN~1\AppData\Local\Temp\{AA2A6F71-E766-4504-BCF3-B64F0857760A}.png" /&gt;&lt;/DIV&gt;</description>
    <pubDate>Mon, 25 Sep 2017 03:15:34 GMT</pubDate>
    <dc:creator>Kelvin_C_</dc:creator>
    <dc:date>2017-09-25T03:15:34Z</dc:date>
    <item>
      <title>About PMU</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/About-PMU/m-p/1130097#M6389</link>
      <description>&lt;P&gt;I'm new to PMU development, I'm curious about the following question about PMU:&lt;/P&gt;

&lt;P&gt;1) I have read&amp;nbsp;IA32_MISC_ENABLE MSR and the bit[7] always is zero , but the bit[12] always set, what does it mean? The CPU is supported PEBS or not supported??&lt;/P&gt;

&lt;P&gt;2) Does PEBS provided the functionality that can trap all of branch , such as , syscall ? what is the basic step for doing this?&lt;/P&gt;

&lt;P&gt;3) without PEBS , I tired to set a PMC0 with&amp;nbsp;Ia32PerfEvtseL0 , and set the PMC0 to be negative number , &amp;nbsp;however, the PMI doesn't happened... why is that..??&lt;/P&gt;

&lt;P&gt;4) I have do a following setting , but there is not PMI generated&lt;/P&gt;

&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="{AA2A6F71-E766-4504-BCF3-B64F0857760A}.png"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/9714i152DBDFCB8754BE2/image-size/large?v=v2&amp;amp;px=999&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="{AA2A6F71-E766-4504-BCF3-B64F0857760A&amp;amp;#125;.png" alt="{AA2A6F71-E766-4504-BCF3-B64F0857760A&amp;amp;#125;.png" /&gt;&lt;/span&gt;&lt;/P&gt;

&lt;P&gt;CPU Model : 60&amp;nbsp;&lt;/P&gt;

&lt;P&gt;where g_Event is 0xC2 and g_mask is 1&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thank you :)&lt;/P&gt;

&lt;DIV&gt;&lt;IMG src="C:\Users\KELVIN~1\AppData\Local\Temp\{AA2A6F71-E766-4504-BCF3-B64F0857760A}.png" /&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 25 Sep 2017 03:15:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/About-PMU/m-p/1130097#M6389</guid>
      <dc:creator>Kelvin_C_</dc:creator>
      <dc:date>2017-09-25T03:15:34Z</dc:date>
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