topic [SOLVED] Safe access to MSR IA32_PRED_CMD in Software Tuning, Performance Optimization & Platform Monitoring

[SOLVED] Safe access to MSR IA32_PRED_CMD

CyrIng — Sat, 02 Nov 2019 12:01:02 GMT

Hello,

In the SDM, the MSR IA32_PRED_CMD (0x49) can be read if CPUID(EAX=07H, ECX=0):EDX[26] equals 1

For example, processor Xeon W3690 of architecture Westmere/Gulftown, microcode version 31, is capable of IBRS & IBPB, according to the EDX register of CPUID leave 7. However, reading the MSR 0x49 will immediately crash processor [whereas MSR IA32_SPEC_CTRL (0x48) works as specified]

FYI, same issue has been encountered with a i7-6700 Skylake processor

Question: what are the discriminant bits to safely read the MSR IA32_PRED_CMD ?

Thank you

Cyril

Registers MSR_IA32_PRED_CMD

CyrIng — Mon, 04 Nov 2019 16:09:54 GMT

Registers MSR_IA32_PRED_CMD and MSR_IA32_FLUSH_CMD are write-only

What kind of crash do you

McCalpinJohn — Tue, 05 Nov 2019 22:39:52 GMT

What kind of crash do you mean? (Cleverly not testing this myself, just in case....)

My driver was seg-faulting

CyrIng — Wed, 06 Nov 2019 06:53:47 GMT

My driver was seg-faulting because reading this MSR. I fixed it by writing only the register.

Thanks! That sounds like the

McCalpinJohn — Wed, 06 Nov 2019 23:19:37 GMT

Thanks! That sounds like the normal fault condition for a non-readable MSR (or for writing to any bits of an MSR that is not writable).

I thought that Intel had configured the "write-only" MSRs to be readable (returning zero), but apparently not all of them!