topic Thank you for the answer. in Software Tuning, Performance Optimization & Platform Monitoring

Broadwell L2 miss stalls count

Vemmou__Marina — Sun, 20 Jan 2019 17:04:33 GMT

Hi,

I'm working on a Broadwell xeon e5-2630 v4, trying to count stall cycles caused by L2 cache misses. In the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, volume 3, under the Broadwell-specific section, there is no mention of the A3h events, such as the CYCLE_ACTIVITY.STALLS_L2_MISS, although this event exists in both earlier (Haswell) and later (Skylake) architectures.

Is it reliable to still try and measure this event in a Broadwell machine? Or is there another way that I can monitor L2 miss stalls?

Yes this event is listed in

Dmitry_R_Intel1 — Tue, 22 Jan 2019 08:34:29 GMT

Yes this event is listed in the event file for Broadwell here: https://download.01.org/perfmon/BDW/broadwell_core_v23.tsv

There should not be any problems with using it.

Thank you for the answer.

Vemmou__Marina — Tue, 22 Jan 2019 21:04:01 GMT

Thank you for the answer.

For earlier (4th generation) processors, the manual says to set cmask for some of the A3h events, but I see no such reference in this document. Do you think I should still set them?

Oh i'm sorry, I just noticed

Vemmou__Marina — Tue, 22 Jan 2019 21:09:49 GMT

Oh i'm sorry, I just noticed there is a counter mask column in the file. Thank you again for the help.