https://community.intel.com/t5/Software-Tuning-Performance/reading-TLB/m-p/1137328#M6563 <P>Hi,</P> <P>For a specific lab experiment involves specific HW issue and timing, I want to avoid page-walking if possible,<BR /> And so I wonder if there is a way (or an intel-specific way such as MSR of some sort), to query the TLB for a specific virtual address' physical address translation, and if that virtual address is not currently in the TLB, or has been invalidated, I'll do the actual page-walking...<BR /> <BR /> This is for a lab experiment so the solution surely can be Intel-specific.<BR /> <BR /> Any ideas?</P> <P>Thanks in advance!</P> <P>David</P> Sun, 30 Sep 2018 02:40:24 GMT Salame__David1 2018-09-30T02:40:24Z https://community.intel.com/t5/Software-Tuning-Performance/reading-TLB/m-p/1137328#M6563 <P>Hi,</P> <P>For a specific lab experiment involves specific HW issue and timing, I want to avoid page-walking if possible,<BR /> And so I wonder if there is a way (or an intel-specific way such as MSR of some sort), to query the TLB for a specific virtual address' physical address translation, and if that virtual address is not currently in the TLB, or has been invalidated, I'll do the actual page-walking...<BR /> <BR /> This is for a lab experiment so the solution surely can be Intel-specific.<BR /> <BR /> Any ideas?</P> <P>Thanks in advance!</P> <P>David</P> Sun, 30 Sep 2018 02:40:24 GMT https://community.intel.com/t5/Software-Tuning-Performance/reading-TLB/m-p/1137328#M6563 Salame__David1 2018-09-30T02:40:24Z