https://community.intel.com/t5/Software-Tuning-Performance/About-MMIO-and-SSE-question/m-p/1159965#M7010 <P>The details may depend on the particular chipset, but the documents I have say that accesses to this space are only allowed to be naturally aligned byte, word, and double-word accesses.</P> Fri, 13 Sep 2019 00:30:54 GMT McCalpinJohn 2019-09-13T00:30:54Z https://community.intel.com/t5/Software-Tuning-Performance/About-MMIO-and-SSE-question/m-p/1159964#M7009 <P>Lately, I tried to map SPIBAR&nbsp;space into virtual address space, and read them. It works well by reps instruction, and normal memory pointer access. However, I ran into a problem that use optimized version of memcpy, it used SSE2 instruction set. The copied content are all&nbsp;0xFF. Why is that happening?</P><P>&nbsp;</P><P>My guess is,&nbsp;device mapped physical memory is different from common physical memory, it&nbsp;doesn't support SSE2 instruction load / store, says, out of width --&gt; so no MMIO is triggered.</P><P>Please correct me if I'm wrong.</P><P>&nbsp;</P><P>&nbsp;</P><P>&nbsp;</P> Tue, 10 Sep 2019 19:11:36 GMT https://community.intel.com/t5/Software-Tuning-Performance/About-MMIO-and-SSE-question/m-p/1159964#M7009 Kelvin_C_ 2019-09-10T19:11:36Z https://community.intel.com/t5/Software-Tuning-Performance/About-MMIO-and-SSE-question/m-p/1159965#M7010 <P>The details may depend on the particular chipset, but the documents I have say that accesses to this space are only allowed to be naturally aligned byte, word, and double-word accesses.</P> Fri, 13 Sep 2019 00:30:54 GMT https://community.intel.com/t5/Software-Tuning-Performance/About-MMIO-and-SSE-question/m-p/1159965#M7010 McCalpinJohn 2019-09-13T00:30:54Z