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    <title>topic Thank you so much. It makes in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161903#M7060</link>
    <description>&lt;P&gt;Thank you so much. It makes sense since hyperthreading is enable in my Linux. I will read the related part you mentioned. Thanks again.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 01 Mar 2019 22:58:39 GMT</pubDate>
    <dc:creator>Zhou__Fang</dc:creator>
    <dc:date>2019-03-01T22:58:39Z</dc:date>
    <item>
      <title>How many MSRs can I use</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161901#M7058</link>
      <description>&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I successfully write event information to MSRs from 0x186 to 0x189. However, I found it returns error starting from address 0x18a.&lt;/P&gt;&lt;P&gt;The CPU I'm using is&amp;nbsp;Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz. I check the developer manual and search online, but find nothing.&lt;/P&gt;&lt;P&gt;Does anyone know how many MSRs can I use? It seems only 4 for my CPU?&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;</description>
      <pubDate>Thu, 28 Feb 2019 19:59:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161901#M7058</guid>
      <dc:creator>Zhou__Fang</dc:creator>
      <dc:date>2019-02-28T19:59:55Z</dc:date>
    </item>
    <item>
      <title>This is documented in Chapter</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161902#M7059</link>
      <description>&lt;P&gt;This is documented in Chapter 18 of the Intel developer manual Volume 3. For your Skylake processor, see Table 18-33. There are 8 general-purpose registers per core. If hyperthreading is enabled, then they are statically partitioned evenly between the two threads of the same core, i.e., each thread has 4 counter registers. So the last valid counter MSR is&amp;nbsp;0x189. This is probably why you're not able to write beyond 0x189. If hyperthreading is disabled, all of the 8 registers are available and so you can address up to MSR 0x18D on each core. Note that if you want to do full-width (48-bit) writes, you have to use the aliasing MSRs starting at 0x4C1.&lt;/P&gt;</description>
      <pubDate>Fri, 01 Mar 2019 20:52:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161902#M7059</guid>
      <dc:creator>HadiBrais</dc:creator>
      <dc:date>2019-03-01T20:52:36Z</dc:date>
    </item>
    <item>
      <title>Thank you so much. It makes</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161903#M7060</link>
      <description>&lt;P&gt;Thank you so much. It makes sense since hyperthreading is enable in my Linux. I will read the related part you mentioned. Thanks again.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 01 Mar 2019 22:58:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/How-many-MSRs-can-I-use/m-p/1161903#M7060</guid>
      <dc:creator>Zhou__Fang</dc:creator>
      <dc:date>2019-03-01T22:58:39Z</dc:date>
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