https://community.intel.com/t5/Software-Tuning-Performance/TLB-Miss-or-Fill-event/m-p/1175004#M7293 <P>1.&nbsp;<SPAN style="font-size: 1em;">Can Haswell CPU take an advantages from TLB MISS Event?</SPAN></P> <P>I would like to measure and intercept which program (instruction) is accessing a physical address , so basically,&nbsp; i would like to do this by intercepting TLB fill, could i do that?</P> <P>Is it impossible since the "skid" problem ?</P> <P>2. I have changed the event and mask to 08H and 02H respectively, can I get the data such as , some information of the TLB VA or PA somethings like that??&nbsp;</P> <P>Kelvin</P> Tue, 19 Dec 2017 08:21:55 GMT Kelvin_C_ 2017-12-19T08:21:55Z https://community.intel.com/t5/Software-Tuning-Performance/TLB-Miss-or-Fill-event/m-p/1175004#M7293 <P>1.&nbsp;<SPAN style="font-size: 1em;">Can Haswell CPU take an advantages from TLB MISS Event?</SPAN></P> <P>I would like to measure and intercept which program (instruction) is accessing a physical address , so basically,&nbsp; i would like to do this by intercepting TLB fill, could i do that?</P> <P>Is it impossible since the "skid" problem ?</P> <P>2. I have changed the event and mask to 08H and 02H respectively, can I get the data such as , some information of the TLB VA or PA somethings like that??&nbsp;</P> <P>Kelvin</P> Tue, 19 Dec 2017 08:21:55 GMT https://community.intel.com/t5/Software-Tuning-Performance/TLB-Miss-or-Fill-event/m-p/1175004#M7293 Kelvin_C_ 2017-12-19T08:21:55Z