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    <title>topic choice of profiling characteristic in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/choice-of-profiling-characteristic/m-p/1180044#M7412</link>
    <description>&lt;P&gt;Sorry for the purely theoretical question.&lt;BR /&gt;
	I think there are great specialists.&lt;BR /&gt;
	I'm interested in your opinion.&lt;/P&gt;

&lt;P&gt;Can I find application characteristics that could describe the behavior&lt;BR /&gt;
	of the application without being bound to a particular processor architecture?&lt;BR /&gt;
	To understand what is the application needs.&lt;/P&gt;

&lt;P&gt;I understand that it's quite stupid to define this as the number of load / store per number&lt;BR /&gt;
	of floating point operations.&lt;/P&gt;

&lt;P&gt;Can I choose the optimal architecture for an application based on this characteristic ?&lt;/P&gt;

&lt;P&gt;Or is everything much more complicated?&lt;/P&gt;

&lt;P&gt;Cache, prefetch, different type of load instructions (load32bit load 64bit and etc),&lt;BR /&gt;
	the degree of parallelism and etc architecture optimizations do this characteristic&lt;BR /&gt;
	is meaningless?&lt;/P&gt;

&lt;P&gt;If so, is it possible to find some characteristics that can be used to determine the&lt;BR /&gt;
	optimal architecture for a given application?&lt;/P&gt;

&lt;P&gt;Is it possible to define these characteristics with the help of counters or should&lt;BR /&gt;
	we consider static analysis for example with the clang/llvm (the intermediate code&lt;BR /&gt;
	is much simpler. For example there is only one type of load / store memory access&lt;BR /&gt;
	instructions, and there are many other simplifications) ?&lt;/P&gt;

&lt;P&gt;Sorry for may be offtop questions and thanks for your time.&lt;/P&gt;</description>
    <pubDate>Sun, 06 May 2018 16:54:36 GMT</pubDate>
    <dc:creator>SB17</dc:creator>
    <dc:date>2018-05-06T16:54:36Z</dc:date>
    <item>
      <title>choice of profiling characteristic</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/choice-of-profiling-characteristic/m-p/1180044#M7412</link>
      <description>&lt;P&gt;Sorry for the purely theoretical question.&lt;BR /&gt;
	I think there are great specialists.&lt;BR /&gt;
	I'm interested in your opinion.&lt;/P&gt;

&lt;P&gt;Can I find application characteristics that could describe the behavior&lt;BR /&gt;
	of the application without being bound to a particular processor architecture?&lt;BR /&gt;
	To understand what is the application needs.&lt;/P&gt;

&lt;P&gt;I understand that it's quite stupid to define this as the number of load / store per number&lt;BR /&gt;
	of floating point operations.&lt;/P&gt;

&lt;P&gt;Can I choose the optimal architecture for an application based on this characteristic ?&lt;/P&gt;

&lt;P&gt;Or is everything much more complicated?&lt;/P&gt;

&lt;P&gt;Cache, prefetch, different type of load instructions (load32bit load 64bit and etc),&lt;BR /&gt;
	the degree of parallelism and etc architecture optimizations do this characteristic&lt;BR /&gt;
	is meaningless?&lt;/P&gt;

&lt;P&gt;If so, is it possible to find some characteristics that can be used to determine the&lt;BR /&gt;
	optimal architecture for a given application?&lt;/P&gt;

&lt;P&gt;Is it possible to define these characteristics with the help of counters or should&lt;BR /&gt;
	we consider static analysis for example with the clang/llvm (the intermediate code&lt;BR /&gt;
	is much simpler. For example there is only one type of load / store memory access&lt;BR /&gt;
	instructions, and there are many other simplifications) ?&lt;/P&gt;

&lt;P&gt;Sorry for may be offtop questions and thanks for your time.&lt;/P&gt;</description>
      <pubDate>Sun, 06 May 2018 16:54:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/choice-of-profiling-characteristic/m-p/1180044#M7412</guid>
      <dc:creator>SB17</dc:creator>
      <dc:date>2018-05-06T16:54:36Z</dc:date>
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