<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: How to use RDSMR/WRMSR at ring 3 in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/How-to-use-RDSMR-WRMSR-at-ring-3/m-p/1247768#M7773</link>
    <description>&lt;P&gt;If you only need to read the core performance counters, then you can do that with the RDPMC instruction at user level if the system configuration bit CR4.PCE is set. &amp;nbsp;&lt;/P&gt;
&lt;P&gt;For Linux systems there is already a kernel device driver interface to allow user-mode programs to request MSR reads or writes. &amp;nbsp;This is implemented in arch/x86/kernel/msr.c in the version of the kernel that I use. &amp;nbsp;&lt;/P&gt;
&lt;P&gt;There is also a project that replicates the kernel MSR infrastructure, but adds whitelisting and other security features --&amp;nbsp;&lt;A href="https://github.com/LLNL/msr-safe" target="_blank"&gt;https://github.com/LLNL/msr-safe&lt;/A&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 19 Jan 2021 16:23:31 GMT</pubDate>
    <dc:creator>McCalpinJohn</dc:creator>
    <dc:date>2021-01-19T16:23:31Z</dc:date>
    <item>
      <title>How to use RDSMR/WRMSR at ring 3</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/How-to-use-RDSMR-WRMSR-at-ring-3/m-p/1245824#M7771</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;I am trying to use rdmsr to read the MSRs&amp;nbsp; like MSR_RAPL_POWER_UNIT, MSR_PP0_ENERGY_STATUS? etc.&amp;nbsp;&lt;/P&gt;
&lt;PRE class="de1"&gt;&lt;SPAN class="kw4"&gt;static&lt;/SPAN&gt; &lt;SPAN class="kw2"&gt;inline&lt;/SPAN&gt; &lt;SPAN class="kw4"&gt;uint64_t&lt;/SPAN&gt; rdmsr&lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;&lt;SPAN class="kw4"&gt;uint64_t&lt;/SPAN&gt; msr&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt;
&lt;SPAN class="br0"&gt;{&lt;/SPAN&gt;
	&lt;SPAN class="kw4"&gt;uint32_t&lt;/SPAN&gt; low&lt;SPAN class="sy0"&gt;,&lt;/SPAN&gt; high&lt;SPAN class="sy0"&gt;;&lt;/SPAN&gt;
	asm &lt;SPAN class="kw4"&gt;volatile&lt;/SPAN&gt; &lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;
		&lt;SPAN class="st0"&gt;"rdmsr"&lt;/SPAN&gt;
		&lt;SPAN class="sy0"&gt;:&lt;/SPAN&gt; &lt;SPAN class="st0"&gt;"=a"&lt;/SPAN&gt;&lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;low&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt;&lt;SPAN class="sy0"&gt;,&lt;/SPAN&gt; &lt;SPAN class="st0"&gt;"=d"&lt;/SPAN&gt;&lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;high&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt;
		&lt;SPAN class="sy0"&gt;:&lt;/SPAN&gt; &lt;SPAN class="st0"&gt;"c"&lt;/SPAN&gt;&lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;msr&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt;
	&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt;&lt;SPAN class="sy0"&gt;;&lt;/SPAN&gt;
	&lt;SPAN class="kw1"&gt;return&lt;/SPAN&gt; &lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;&lt;SPAN class="br0"&gt;(&lt;/SPAN&gt;&lt;SPAN class="kw4"&gt;uint64_t&lt;/SPAN&gt;&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt;high &lt;SPAN class="sy0"&gt;&amp;lt;&amp;lt;&lt;/SPAN&gt; &lt;SPAN class="nu0"&gt;32&lt;/SPAN&gt;&lt;SPAN class="br0"&gt;)&lt;/SPAN&gt; &lt;SPAN class="sy0"&gt;|&lt;/SPAN&gt; low&lt;SPAN class="sy0"&gt;;&lt;/SPAN&gt;
&lt;SPAN class="br0"&gt;}&lt;/SPAN&gt;&lt;/PRE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I understand that reading and writing a MSR should not possible from user space and when I run the above function it showed "segmentation fault". So, I would like know if I can create a kernel module in order to enable the rdmsr/wrmsr for the ring 3 ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Side note: this code source is to enable the rdpmc&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/softdevteam/user_rdpmc" target="_blank"&gt;https://github.com/softdevteam/user_rdpmc&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you for your time.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Fadel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 13 Jan 2021 10:20:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/How-to-use-RDSMR-WRMSR-at-ring-3/m-p/1245824#M7771</guid>
      <dc:creator>Fadel</dc:creator>
      <dc:date>2021-01-13T10:20:42Z</dc:date>
    </item>
    <item>
      <title>Re: How to use RDSMR/WRMSR at ring 3</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/How-to-use-RDSMR-WRMSR-at-ring-3/m-p/1247768#M7773</link>
      <description>&lt;P&gt;If you only need to read the core performance counters, then you can do that with the RDPMC instruction at user level if the system configuration bit CR4.PCE is set. &amp;nbsp;&lt;/P&gt;
&lt;P&gt;For Linux systems there is already a kernel device driver interface to allow user-mode programs to request MSR reads or writes. &amp;nbsp;This is implemented in arch/x86/kernel/msr.c in the version of the kernel that I use. &amp;nbsp;&lt;/P&gt;
&lt;P&gt;There is also a project that replicates the kernel MSR infrastructure, but adds whitelisting and other security features --&amp;nbsp;&lt;A href="https://github.com/LLNL/msr-safe" target="_blank"&gt;https://github.com/LLNL/msr-safe&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 19 Jan 2021 16:23:31 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/How-to-use-RDSMR-WRMSR-at-ring-3/m-p/1247768#M7773</guid>
      <dc:creator>McCalpinJohn</dc:creator>
      <dc:date>2021-01-19T16:23:31Z</dc:date>
    </item>
  </channel>
</rss>

