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    <title>topic VTune: Compare row-buffer locality of two programs in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/VTune-Compare-row-buffer-locality-of-two-programs/m-p/1317370#M7945</link>
    <description>&lt;P&gt;I wish to show that a certain optimization makes a program stall less due to improved row-buffer locality (DRAM). I looked at all the VTune metrics. There are a couple of metrics that talk about memory-bandwidth stalls and memory-bound, store-bound, etc.&lt;/P&gt;
&lt;P&gt;I'm not sure which metric to use for my purpose. Any comments will be helpful.&lt;/P&gt;
&lt;P&gt;Thanks&lt;/P&gt;</description>
    <pubDate>Mon, 27 Sep 2021 06:22:31 GMT</pubDate>
    <dc:creator>HarshVardhanKumar</dc:creator>
    <dc:date>2021-09-27T06:22:31Z</dc:date>
    <item>
      <title>VTune: Compare row-buffer locality of two programs</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/VTune-Compare-row-buffer-locality-of-two-programs/m-p/1317370#M7945</link>
      <description>&lt;P&gt;I wish to show that a certain optimization makes a program stall less due to improved row-buffer locality (DRAM). I looked at all the VTune metrics. There are a couple of metrics that talk about memory-bandwidth stalls and memory-bound, store-bound, etc.&lt;/P&gt;
&lt;P&gt;I'm not sure which metric to use for my purpose. Any comments will be helpful.&lt;/P&gt;
&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Mon, 27 Sep 2021 06:22:31 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/VTune-Compare-row-buffer-locality-of-two-programs/m-p/1317370#M7945</guid>
      <dc:creator>HarshVardhanKumar</dc:creator>
      <dc:date>2021-09-27T06:22:31Z</dc:date>
    </item>
    <item>
      <title>Re: VTune: Compare row-buffer locality of two programs</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/VTune-Compare-row-buffer-locality-of-two-programs/m-p/1317560#M7948</link>
      <description>&lt;P&gt;For the server processors, the performance counters in the IMC support events that can be used to measure open-page and closed-page accesses. &amp;nbsp;The nomenclature differs a bit from what I have seen elsewhere in the industry, but it is not hard to translate.&lt;/P&gt;
&lt;P&gt;In the Xeon systems at the Texas Advanced Computer Center, we program the four IMC performance counters on each DDR4 channel to measure:&amp;nbsp;&lt;/P&gt;
&lt;OL&gt;
&lt;LI&gt;CAS_COUNT.RD &amp;nbsp;-- all DRAM read accesses&lt;/LI&gt;
&lt;LI&gt;CAS_COUNT.WR -- all DRAM write accesses&lt;/LI&gt;
&lt;LI&gt;ACT_COUNT.ALL -- all DRAM ACTIVATE commands&lt;/LI&gt;
&lt;LI&gt;PRE_COUNT.PAGE_MISS -- all DRAM pages closed due to row conflict&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;The formulas for converting these four values to the page hit and miss rates are included in the uncore performance monitoring reference manual for each server processor.&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Page Conflict ratio = PRE_COUNT.PAGE_MISS / (CAS_COUNT.RD + CAS_COUNT.WR)&lt;/LI&gt;
&lt;LI&gt;Page Empty ratio = (ACT_COUNT.ALL - PRE_COUNT.PAGE_MISS) /&amp;nbsp;(CAS_COUNT.RD + CAS_COUNT.WR)&lt;/LI&gt;
&lt;LI&gt;Page Hit ratio = 1 - PageConflictRatio - PageEmptyRatio&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;These counters appear to be reliable on all the systems I have tested, but finding useful information in the values is challenging.&lt;/P&gt;</description>
      <pubDate>Mon, 27 Sep 2021 22:01:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/VTune-Compare-row-buffer-locality-of-two-programs/m-p/1317560#M7948</guid>
      <dc:creator>McCalpinJohn</dc:creator>
      <dc:date>2021-09-27T22:01:27Z</dc:date>
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