https://community.intel.com/t5/Software-Tuning-Performance/Invalidation-of-the-cache-from-L1-cache/m-p/1363426#M8016 <P>The exact same question was answered on stackoverflow 4 days before the question was repeated here.</P> <P><A href="https://stackoverflow.com/questions/71067471/invalidation-of-the-cache-from-l1-cache/" target="_blank">https://stackoverflow.com/questions/71067471/invalidation-of-the-cache-from-l1-cache/</A></P> <P>&nbsp;</P> Thu, 24 Feb 2022 16:45:37 GMT McCalpinJohn 2022-02-24T16:45:37Z https://community.intel.com/t5/Software-Tuning-Performance/Invalidation-of-the-cache-from-L1-cache/m-p/1360608#M8009 <DIV> <P>Suppose that a cache line with Variable X is simultaneously uploaded to L1d of CPU0 and L1d of CPU1. After changing the value of X from CPU0, when CPU1's L1d Cache Line is invalidated<A href="https://www.olansinl.com" target="_self">.</A> Is it impossible for CPU1 to copy the variable X from CPU0's L1d cache if CPU0 has a cache line with X? And even if this is not the case, I want to know if there are cases where CPU0 brings in CPU1'</P> </DIV> <DIV> <DIV> <DIV>&nbsp;</DIV> </DIV> </DIV> Tue, 15 Feb 2022 19:35:14 GMT https://community.intel.com/t5/Software-Tuning-Performance/Invalidation-of-the-cache-from-L1-cache/m-p/1360608#M8009 realbencutting 2022-02-15T19:35:14Z https://community.intel.com/t5/Software-Tuning-Performance/Invalidation-of-the-cache-from-L1-cache/m-p/1363426#M8016 <P>The exact same question was answered on stackoverflow 4 days before the question was repeated here.</P> <P><A href="https://stackoverflow.com/questions/71067471/invalidation-of-the-cache-from-l1-cache/" target="_blank">https://stackoverflow.com/questions/71067471/invalidation-of-the-cache-from-l1-cache/</A></P> <P>&nbsp;</P> Thu, 24 Feb 2022 16:45:37 GMT https://community.intel.com/t5/Software-Tuning-Performance/Invalidation-of-the-cache-from-L1-cache/m-p/1363426#M8016 McCalpinJohn 2022-02-24T16:45:37Z