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    <title>topic MLC option to print a cache line content in Software Tuning, Performance Optimization &amp; Platform Monitoring</title>
    <link>https://community.intel.com/t5/Software-Tuning-Performance/MLC-option-to-print-a-cache-line-content/m-p/1488657#M8178</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am a MLC tool user. I would like to know if MLC has any option to print the contents of a cache line? I am aware of the -M option to provide a pattern_file to initialize the buffer with specific data.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there a MLC option to print the read data as well? Please clarify.&lt;/P&gt;</description>
    <pubDate>Tue, 23 May 2023 02:56:43 GMT</pubDate>
    <dc:creator>DeepikaGanga</dc:creator>
    <dc:date>2023-05-23T02:56:43Z</dc:date>
    <item>
      <title>MLC option to print a cache line content</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MLC-option-to-print-a-cache-line-content/m-p/1488657#M8178</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am a MLC tool user. I would like to know if MLC has any option to print the contents of a cache line? I am aware of the -M option to provide a pattern_file to initialize the buffer with specific data.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there a MLC option to print the read data as well? Please clarify.&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2023 02:56:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MLC-option-to-print-a-cache-line-content/m-p/1488657#M8178</guid>
      <dc:creator>DeepikaGanga</dc:creator>
      <dc:date>2023-05-23T02:56:43Z</dc:date>
    </item>
    <item>
      <title>Re: MLC option to print a cache line content</title>
      <link>https://community.intel.com/t5/Software-Tuning-Performance/MLC-option-to-print-a-cache-line-content/m-p/1499134#M8185</link>
      <description>&lt;P&gt;Deepika,&lt;/P&gt;&lt;P&gt;There is no such option to print the content of the cache lines. However, the content of the cache lines should not matter for the latency of the access. Only the access pattern should be relevant for that.&lt;/P&gt;&lt;P&gt;Kind regards&lt;/P&gt;&lt;P&gt;Thomas&lt;/P&gt;</description>
      <pubDate>Mon, 26 Jun 2023 13:07:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Software-Tuning-Performance/MLC-option-to-print-a-cache-line-content/m-p/1499134#M8185</guid>
      <dc:creator>Thomas_W_Intel</dc:creator>
      <dc:date>2023-06-26T13:07:50Z</dc:date>
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