Question about cache consistency when using DDIO(DCA)

Hoddy — Tue, 30 Jan 2024 07:39:40 GMT

Hi,

I perform some tests on DDIO and find the Page 8 in PPT (https://www.dpdk.org/event/dpdk-summit-china-2018/roman-sudarikov-dpdk_prc_summit_sudarikov/) about controlling DDIO.

I did observe performance changes by modifying the configurations of registers in the same way as Option 1, 2 and 3 in the PPT, so I feel these are correct.

It shows that when set the "Disable_all_allocating_flows" to "0" and "NoSnoopOpWrEn" to 1, it is possible to control the DDIO per PCI Transaction by changing "TLP NS Bit" (e.g. setting this Bit to "0" to enable DDIO). However, this approach turns off "Snoop" ("NoSnoopOpWrEn" to 1)

I wonder that, is this "Snoop" a snooping protocol to guarantee consistency between cache and DRAM? If so, accoding to Option 4 and 5 in the PPT, if I first write object using version One to LLC with "TLP NS bit" set to 0 (i.e., DDIO on), and then write the same object using version Two to DRAM with "TLP NS bit" set to 1 (i.e., DDIO off), will this cause the object in the DRAM to be newer than that in the LLC?

Best Regrads

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Question about cache consistency when using DDIO(DCA)