https://community.intel.com/t5/Software-Tuning-Performance/Intel-Processor-Trace/m-p/1567491#M8305 <P>I am having a hard time to understand the following text from the SDM (Section 33.3.6):</P><P>&nbsp;</P><P>"TSC packets are generated when there is insufficient information to reconstruct wall-clock time, due to tracing&nbsp;being disabled (TriggerEn=0), or power down scenarios like a transition to a deep-sleep MWAIT C-state. In this&nbsp;case, the CYC that is generated along with the TSC will indicate the number of cycles actively tracing (those&nbsp;powered up, with TriggerEn=1) executed between the last CYC packet and the TSC packet. And hence the amount&nbsp;of time spent while tracing is inactive can be inferred from the difference in time between that expected based on&nbsp;the CYC value, and the actual time indicated by the TSC."</P><P>&nbsp;</P><P>How exactly can one compute the inactive period? The text "... from the difference in time between that expected based on&nbsp;the CYC value ..." confuses me a lot. Can one give an example?</P><P>&nbsp;</P><P>&nbsp;</P> Tue, 30 Jan 2024 14:37:42 GMT Bogdan21 2024-01-30T14:37:42Z https://community.intel.com/t5/Software-Tuning-Performance/Intel-Processor-Trace/m-p/1567491#M8305 <P>I am having a hard time to understand the following text from the SDM (Section 33.3.6):</P><P>&nbsp;</P><P>"TSC packets are generated when there is insufficient information to reconstruct wall-clock time, due to tracing&nbsp;being disabled (TriggerEn=0), or power down scenarios like a transition to a deep-sleep MWAIT C-state. In this&nbsp;case, the CYC that is generated along with the TSC will indicate the number of cycles actively tracing (those&nbsp;powered up, with TriggerEn=1) executed between the last CYC packet and the TSC packet. And hence the amount&nbsp;of time spent while tracing is inactive can be inferred from the difference in time between that expected based on&nbsp;the CYC value, and the actual time indicated by the TSC."</P><P>&nbsp;</P><P>How exactly can one compute the inactive period? The text "... from the difference in time between that expected based on&nbsp;the CYC value ..." confuses me a lot. Can one give an example?</P><P>&nbsp;</P><P>&nbsp;</P> Tue, 30 Jan 2024 14:37:42 GMT https://community.intel.com/t5/Software-Tuning-Performance/Intel-Processor-Trace/m-p/1567491#M8305 Bogdan21 2024-01-30T14:37:42Z