topic Re:Disabling particular llc slices? in Software Tuning, Performance Optimization & Platform Monitoring

Disabling particular llc slices?

huangwentao — Mon, 03 Jun 2024 02:06:38 GMT

I have a Sapphire Rapids processor, Xeon 6430 gold. I am running my whole system in sub-numa clustering mode, and I would like to disable particular last level slices (LLCs) in my system if possible. For instance, I would like to disable LLCs for core 0--7, is there any ways to do so?

I have tried to do this via Intel cache allocation technology (via pqos) and also model-specific registers (MSR), both of which try to control cache ways. However, I find it is not allowed to set the cache ways to complete 0, (e.g., "sudo wrmsr -p 0 0xC90 0x0000"). Are there any other ways to fully disable specific LLCs?

Thank you.

Re:Disabling particular llc slices?

NormanS_Intel — Wed, 05 Jun 2024 01:58:24 GMT

Hello huangwentao,

Thank you for posting in the community!

To ensure you receive the most specialized assistance, we have a dedicated forum that addresses these specific concerns. Therefore, I will be moving this discussion to our Server Forum. This will allow our knowledgeable community and experts to provide you with timely and accurate solutions.

Best regards,

Norman S.

Intel Customer Support Engineer

Re: Re:Disabling particular llc slices?

huangwentao — Fri, 07 Jun 2024 09:17:13 GMT

Hi Norman,

Please help move it to Server Forum, thank you.

Wentao

Re: Disabling particular llc slices?

McCalpinJohn — Sat, 08 Jun 2024 22:57:16 GMT

I don't recall seeing any Intel features that allow enabling/disabling L3 cache slices in any of the mesh-based processors.

None of the processors I have investigated are configured with a disabled CHA/SF/LLC slice at the same location as an enabled core.

Changing the number of enabled L3 slices would require a change in the hash function that maps addresses to the active slices. (These mapping functions are discussed in https://dx.doi.org/10.26153/tsw/14539). The selection of the mapping function might be fused into the chip at manufacturing time?

Changing the locations of enabled L3 slices would require a change in the routing tables that contain the physical locations of the logical L3 slice numbers. These tables might be fused in at manufacturing time or constructed very early in the boot process (by confidential/secret/undocumented code).

Re: Disabling particular llc slices?

huangwentao — Sun, 09 Jun 2024 06:14:21 GMT

Dear John,

Noted with thanks.

Wentao