topic Intel PCM - Is there mistake on atom? in Software Tuning, Performance Optimization & Platform Monitoring

Intel PCM - Is there mistake on atom?

GHui — Tue, 14 Feb 2012 03:17:47 GMT

On selevt, its setting is
coreEventDesc[0].event_number = ARCH_LLC_REFERENCE_EVTNR;
coreEventDesc[0].umask_value = ARCH_LLC_REFERENCE_UMASK;
coreEventDesc[1].event_number = ARCH_LLC_MISS_EVTNR;
coreEventDesc[1].umask_value = ARCH_LLC_MISS_UMASK;

On pcm, its setting is
msr->read(IA32_PMC0, &cL3Miss); // for Atom mapped to ArchLLCRef field
msr->read(IA32_PMC1, &cL3UnsharedHit); // for Atom mapped to ArchLLCMiss field

I think pmc0 and pmc1 are mistake for each other.

Intel PCM - Is there mistake on atom?

Roman_D_Intel — Tue, 14 Feb 2012 10:39:04 GMT

GHui,

that is not a mistake. The variables are mapped to other names depending on architecture (using a C++ union):

[cpp]    union {
        uint64 L3Miss;
        uint64 Event0;
        uint64 ArchLLCRef;
    };
    union {
        uint64 L3UnsharedHit;
        uint64 Event1;
        uint64 ArchLLCMiss;
    };[/cpp]

Thethe L3Miss and the ArchLLCRef are mapped to the same address and L3UnsharedHit/ArchLLCMissare both mapped to a different address. This is done to have the same class namefor objects storing event counts (*CounterState) on independently of the processor architecture and simultaneously save space by reusing the memory. The functions that compute cache metrics are using the ArchLLCRef/ArchLLCMiss names on Atom. In my opiniona different solution withseparate custom implementation classes for each architecture would add more complexity and explode the code size (many architectures have just a small differences that are easy to handle without a code bloat).

Roman

Intel PCM - Is there mistake on atom?

GHui — Wed, 15 Feb 2012 02:54:59 GMT

Thank you for your correcting.
The result that LLC_Miss/LLC_Ref is easy to understand. LLC_Miss/LLC_Ref means LLC miss ratio.
The perfevtsel0 is setting LLC_Reference event, while store value which read from pcm0 to cL3Miss, although it mapped to ArchLLCRef field. I'm really puzzled for this.
Is there any meaning that put L3Miss and ArchLLCRef to the same union, why not put L3Miss and ArchLLCMiss to the same union?

Intel PCM - Is there mistake on atom?

Roman_D_Intel — Wed, 15 Feb 2012 08:49:27 GMT

GHui,

you are right. It seems it makes more senseto change the union structures as you proposed.

Thanks,
Roman