Question about Icelake IIO Uncore IOTLB & PWC Performance Counters

Leshna — Thu, 17 Jul 2025 01:23:43 GMT

I'm working with the uncore performance counters on an Intel Xeon Scalable processor (Icelake) and have a few questions about the IOTLB events, specifically those in Table 2-184 of the performance monitoring guide:

How can I measure Page Walk Cache (PWC) misses? The manual provides events for PWC_<size>_HITS. Since multiple lookups can hit for a single page walk, simply subtracting hits from lookups doesn't seem reliable for calculating misses. Is there a way to count PWC misses or even total lookups at each specific cache level level ?
What is a "transaction" for the FIRST_LOOKUPS IOTLB event? The definition states it "Counts the first time a request looks up IOTLB." Is a single read/write request from a PCIe device considered one transaction is it just a single PCIe TLP?
What is the function of the 4K-level PWC counter? The spec mentions the PWC caches higher-level page table entries (PML4E, PDPE, PDE). Does the 4K-level PWC act as a cache for the final Page Table Entries (PTEs)? Then would it just not do the work as a extended TLB? Does every IOTLB miss always go through this 4 K‑level cache before walking higher levels?

topic Question about Icelake IIO Uncore IOTLB & PWC Performance Counters in Software Tuning, Performance Optimization & Platform Monitoring

Question about Icelake IIO Uncore IOTLB & PWC Performance Counters