Can multiple wide-band data modems be implemented per FPGA?

EHall8 — Wed, 13 Feb 2019 04:43:28 GMT

I am studying what FPGA resources are needed to implement multiple modems for multiple mm-wave backhaul wireless links with each modem similar to the one described here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-mobile-backhaul.pdf

Each data link would need to carry 3 Gbps at E-band in a 0.5 or 1 GHz RF bandwidth. Can more than one Gbps modem be implemented in the Arria V, Stratix V, or Arria 10 FPGA options shown in the design example? Does anyone know of a table that shows the number of modems that can be implemented in the various FPGA device types?

Thank you for your ideas!

Re: Can multiple wide-band data modems be implemented per FPGA?

David_V_Intel — Thu, 14 Feb 2019 05:05:21 GMT

Hello EHall8, We apologize for the inconvenience, but all support is via web. We can provide you with the links and information provided to us, but you will need to go to the web and find the assistance you need there. Please go to Intel.com > select FPGA and Programmable Devices > then All FPGA & Programmable Devices > From the list you can see most of the products and below that additional options such as Documentation, How to Buy and the FPGA Product Selector. Below are the available options for purchasing FPGA and Programmable Devices: How to Buy: https://www.intel.com/content/www/us/en/programmable/buy.html Intel® Authorized Distributors and Approved Suppliers https://www.intel.com/content/www/us/en/partner/where-to-buy/overview.html You can always create a thread in our support forums for inquiries of the product if needed: https://forums.intel.com/s/topic/0TO0P000000MWKBWA4/programmable-devices?language=en_US Regards, David V Intel Customer Support Technician Under Contract to Intel Corporation

topic Re: Can multiple wide-band data modems be implemented per FPGA? in Wireless

Can multiple wide-band data modems be implemented per FPGA?

Re: Can multiple wide-band data modems be implemented per FPGA?