<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic AX200 Platform side Design Question in Wireless</title>
    <link>https://community.intel.com/t5/Wireless/AX200-Platform-side-Design-Question/m-p/1216008#M31180</link>
    <description>&lt;P&gt;I am designing the platform-side board that will use the AX200 M.2 2230 module. We will only be using the WLAN functionality, and I wanted to clarify a few pins/signal listed in the External product specification (document number 598183-1.8).&lt;BR /&gt;- If bluetooth is not being used, can the coexist signals (pins 44,46,48) be left unconnected on the platform side?&lt;BR /&gt;- Can you please confirm that only a single PCIe lane is used, and the second lane (pins, 59, 61, 65, 67) are not used?&lt;BR /&gt;- Can you confirm that the I2C/UART signals (pins 58, 60, 62, 64) are not used on the AX200 and can be left unconnected on the platform side.?&lt;/P&gt;
&lt;P&gt;Thank you for your assistance.&lt;/P&gt;</description>
    <pubDate>Thu, 08 Oct 2020 18:58:14 GMT</pubDate>
    <dc:creator>RMahar_Vanteon</dc:creator>
    <dc:date>2020-10-08T18:58:14Z</dc:date>
    <item>
      <title>AX200 Platform side Design Question</title>
      <link>https://community.intel.com/t5/Wireless/AX200-Platform-side-Design-Question/m-p/1216008#M31180</link>
      <description>&lt;P&gt;I am designing the platform-side board that will use the AX200 M.2 2230 module. We will only be using the WLAN functionality, and I wanted to clarify a few pins/signal listed in the External product specification (document number 598183-1.8).&lt;BR /&gt;- If bluetooth is not being used, can the coexist signals (pins 44,46,48) be left unconnected on the platform side?&lt;BR /&gt;- Can you please confirm that only a single PCIe lane is used, and the second lane (pins, 59, 61, 65, 67) are not used?&lt;BR /&gt;- Can you confirm that the I2C/UART signals (pins 58, 60, 62, 64) are not used on the AX200 and can be left unconnected on the platform side.?&lt;/P&gt;
&lt;P&gt;Thank you for your assistance.&lt;/P&gt;</description>
      <pubDate>Thu, 08 Oct 2020 18:58:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Wireless/AX200-Platform-side-Design-Question/m-p/1216008#M31180</guid>
      <dc:creator>RMahar_Vanteon</dc:creator>
      <dc:date>2020-10-08T18:58:14Z</dc:date>
    </item>
    <item>
      <title>Re:AX200 Platform side Design Question</title>
      <link>https://community.intel.com/t5/Wireless/AX200-Platform-side-Design-Question/m-p/1216321#M31203</link>
      <description>&lt;P&gt;RMahar_Vanteon, Thank you for posting in the Intel® Communities Support.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;In reference to this topic, in order for us to provide the most accurate assistance on this matter, please visit, sign-in and submit your inquiry in our Intel® Resource and Design Center site, they will further assist you in there in trying to provide the information you are looking for:&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/design/resource-design-center.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/design/resource-design-center.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Any questions, please let me know.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Albert R.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&lt;/P&gt;&lt;P&gt;A Contingent Worker at Intel&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 09 Oct 2020 18:53:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Wireless/AX200-Platform-side-Design-Question/m-p/1216321#M31203</guid>
      <dc:creator>Alberto_Sykes</dc:creator>
      <dc:date>2020-10-09T18:53:09Z</dc:date>
    </item>
  </channel>
</rss>

