Branch misprediction hardware event not working for Intel Core 2 Duo CPU: T7300

[sandeshnie]

Hardware events like BR_CND_MISSP_EXEC, BR_IND_MISSP_EXEC, BR_INST_RETIRED.MISPRED, BR_RET_MISSP_EXEC are not getting updated even if I run a code with 4000 branches in it.

Could anyone suggest what is the Issue behind this. Is it that this processor varient is not supported by vtune?

Any help is greatly appreciated.

[Peter_W_Intel]

Assume that you are using VTune Amplifier XE 2011 Update 4.

You can use predefined analysis type "General Exploration", which includes event BP_MISSP_EXEC, and CPU_CLK_UNHALTED.CORE. The report will report Branch Misprediction ratio automatically.

-OR-

You also can create a new Custom Analysis - select new hardware events analysis for Intel? Core 2 Duo processor:
BR_MISSP_EXEC
BR_INST_RETIRED.ANY
CPU_CLK_UNHALTED.CORE

You canevaluate ratio BP_MISSP_EXEC/BR_INST_RETIRED.ANY manually to knowaverage missesper branchexecuting

You can evaluate ratio BP_MISSP_EXEC*(CPU_Frequency/CPU_CLK_UNHALTED.CORE) to knowaverage missesper second

Regards, Peter

[sandeshnie]

Hi Peter,

I used General Exploration Analysis and still found the same results. The branch mispredict column is showing as 0.001, which is not right according to me. As my code includes 4000 branches placed at regular intervals I believe that it should generate mispredictions.

I also tested on one more varient of core 2 duo processor-T6600, results of which I have attached with this post.

I also tested the same using LightWeight hotspot Analysis but I am getting the same results.

Thanks,

Sandesh

[Peter_W_Intel]

Thanks for your screen shots.

I think that results are correct. Branch Misprediction is low

Miss rate for = 4,000,000 (BTB missed) / 4,124,000,000 (branch executed) = 0.001

You needn't doany improvement on this hand.

Regards, Peter

[sandeshnie]

Hi Peter,

My algorithm is as follows:

while(i<1000,000){

1st branch

.

.

2nd branch

.

.

3rd branch

.

.

.

.

.

.

4000 branches

} // iterate 1million times.

So ideally this should result in misprediction as far as I know.

Because the total number of branches the processor can hold in its buffer may not be > 2000.

Waiting for your response. Let me know if I need to provide any further information.

[Peter_W_Intel]

The resultdepends on I-Cache line size, BTB buffer size, and gap sizebetween two branches...especially if you use PGO switches from Intel C++ compiler (or high-frequent use for top 1-2-3 branches), that can avoid high rate of Branch Misprediction.

If you still have concerns - please go https://premier.intel.com to submit a ticket with simple test case.

Regards, Peter