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DE1_SOC_ADA Question

DE1SOCman
Beginner
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Hello, I'm trying to connect DE1_SOC and THDB-ADA in Korea, so I'm trying to output a sawtooth wave in DAC_DA and a triangular wave in DAC_DB

However, as shown in the attached picture, I am inquiring because the output is from the signal tap logic analyzer as a digital model. I am attaching the code below and attaching the picture.

Please review if I missed anything. Thank you.

 

module DE1_SOC(
// Clock and Reset
input CLOCK_50,

// DAC Signals
output [13:0] DAC_DA, // Sawtooth wave output
output [13:0] DAC_DB, // Ramp wave starting from 3FFF
output DAC_CLK_A,
output DAC_CLK_B,
output DAC_MODE,
output DAC_WRT_A,
output DAC_WRT_B,
output DAC_RST,
output DAC_SLEEP,

// Debug LEDs
output [9:0] LEDR
);

// Internal Registers
reg [13:0] sawtooth_wave_A; // Sawtooth for channel A
reg [13:0] ramp_wave_B; // Ramp for channel B starting from 3FFF
reg [15:0] counter_sawtooth;
reg [15:0] counter_ramp;
reg [15:0] freq_divider;

// DAC Control Registers
reg DAC_WRT_A_reg;
reg DAC_WRT_B_reg;
reg dac_initialized;
reg [3:0] init_state;

// Added internal registers for DAC_RST and DAC_SLEEP
reg dac_rst_reg;
reg dac_sleep_reg;

// Debug Counter
reg [25:0] led_counter;

// DAC Initialization Sequence
always @(posedge CLOCK_50) begin
// Initialization Logic
if (!dac_initialized) begin
case (init_state)
4'd0: begin
dac_rst_reg <= 1'b0;
dac_sleep_reg <= 1'b1;
init_state <= init_state + 1;
end
4'd1: begin
dac_rst_reg <= 1'b1;
dac_sleep_reg <= 1'b0;
init_state <= init_state + 1;
end
4'd2: begin
dac_initialized <= 1'b1;
end
endcase
end

// Frequency Divider
freq_divider <= freq_divider + 1;

// Sawtooth Wave Generation for Channel A (0 to 3FFF)
if (freq_divider[12]) begin // Adjust the frequency divider for desired timing
counter_sawtooth <= counter_sawtooth + 1;
if (counter_sawtooth >= 14'd16383)
counter_sawtooth <= 0;
sawtooth_wave_A <= counter_sawtooth[13:0];
end

// Ramp Wave Generation for Channel B (3FFF decrementing)
if (freq_divider[12]) begin // Adjust the frequency divider for desired timing
if (counter_ramp > 0) begin
counter_ramp <= counter_ramp - 1;
end else begin
counter_ramp <= 14'h3FFF; // Reset to max value
end
ramp_wave_B <= counter_ramp[13:0];
end

// DAC Write Signal Generation
if (freq_divider == 16'h0) begin
DAC_WRT_A_reg <= 1'b1;
end else if (freq_divider == 16'h8000) begin
DAC_WRT_A_reg <= 1'b0;
end

if (freq_divider == 16'h4000) begin
DAC_WRT_B_reg <= 1'b1;
end else if (freq_divider == 16'hC000) begin
DAC_WRT_B_reg <= 1'b0;
end

// LED Debug Counter
led_counter <= led_counter + 1;
end

// Output Assignments
assign DAC_DA = sawtooth_wave_A; // Sawtooth on Channel A
assign DAC_DB = ramp_wave_B; // Ramp starting from 3FFF on Channel B
assign DAC_CLK_A = CLOCK_50;
assign DAC_CLK_B = CLOCK_50;
assign DAC_MODE = 1'b0;
assign DAC_WRT_A = DAC_WRT_A_reg;
assign DAC_WRT_B = DAC_WRT_B_reg;

// DAC Control Assignments
assign DAC_RST = dac_rst_reg;
assign DAC_SLEEP = dac_sleep_reg;

// Debug LED Assignments
assign LEDR[0] = dac_initialized;
assign LEDR[1] = DAC_WRT_A_reg;
assign LEDR[2] = led_counter[25];
assign LEDR[9:3] = 7'b0;

endmodule

DE1SOCman_0-1733905703073.png

 

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