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himura3
Beginner
180 Views

Does vtune support Xeon 7140M?

Hello

I using Vtune 9.0 for windows on Xeon 7140M processors.

In spite of many 2nd-Level Cache Read Miss, no 3rd-Level Cache Read Referenceis detected by vtune.

Can vtune detect 3rd-Level cache read reference and miss of Xeon 7140M?

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5 Replies
aokunev
Beginner
180 Views

Hi

VTune sampling does not yet support collection onuncore events, like one you've tried to collect. The processor configuration XML files andVTune documentation needs to be updated to remove those events until it's implemented.

Andrei
himura3
Beginner
180 Views

Hi

Thank you Andrei.

I have one more question.

Do you know the difference between 2nd-Level Cache Read Misses and
2nd-Level Cache Load Misses Retired?

TimP
Black Belt
180 Views

My belief has been that Misses Retired doesn't count duplicate misses which occur while waiting for the first miss to be resolved. If this is not so, I too would like a better explanation.
What about misses which occur on a mis-predicted branch, or misses which are dropped when they cross page boundaries? I expect those to be relatively infrequent, but it might be interesting to know how they are counted.
Evgueny_K_Intel
Employee
180 Views

According to processor manual

2

nd-Level Cache Load Misses Retired = The number of retired load ops that experienced 2nd-Level cache misses.

2

nd-Level Cache Read Misses = The number of 2nd-level cache read misses (load and RFO misses).

So 2nd-Level Cache Load Misses Retired show how many times load instructions failed to find data in L2;

2nd-Level Cache Read Misses show how many times cache miss occured in L2 due to multiple reasons. In case if you are working on optimization of memory access, particularly want to keep data in cache, I'd recommend monitoring 2nd-Level Cache Load Misses Retired - this is exactly about reading data and most stalls are due to misses in attempt of loading data, stalls on writing are much hidden by processor.

Your explanation fits well for Core 2 Duo processor. There

MEM_LOAD_RETIRED.L2_MISS is total # of misses including duplicates, and

MEM_LOAD_RETIRED.L2_LINE_MISS excludes duplicates

himura3
Beginner
180 Views

Do you mean
2nd-Level Cache Load Misses Retired =counts load instructions that experienced 2nd-Level cache.
2nd-Level Cache Read Misses =counts load + store +other instructions that experienced 2nd-Level cache.
?

In my results,

some processes have more 2nd-Level Cache Load Misses Retiredthan 2nd-Level Cache Read Misses.

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