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Hi,
I've been profiling an application and found that the value for the "RS full Ratio" metric is quite high (around 94%). Can this be normal in some cases or it really indicates that there is some performance issue? And if there is indeed a problem, do you have any advices on how to solve it?
Metrics:
CPI: 6,618
RS Full Ratio:94,01%
ROB Full Ratio:2,63%
Load or Store Buffer Full Ratio: 0,03%
L2 Cache Miss Rate: 3,10%
TLB miss penalty: 19,43%
Instruction Fetch Stall: 0,14%
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That and the TLB miss appear likely to be symptoms of a performance problem. It seems likely you would need to drill down and localize the problem, possibly see if any other events shed light. High TLB miss rate likely means that you don't use enough of the contents of each cache line; memory references are too scattered. Yet, it seems the L2 cache locality is good. If running on an architecture where 2 levels of TLB miss counters are available, you might want to collect both to verify that you have a problem only with L1 TLB. Also investigate other resource stall events, if identifying the responsible source code doesn't clarify it.

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