Ok, this is P4 microarchitecture. Both events indicate L2 cache mises, but different portions.
2nd-level Cache Load Misses Retired is measured inside cache unit and counts the number of retired instructions that attempted to load data from the 2nd-level cache (with no success). This is not a complete count as there might be another reasons for L2 cache misses.
2nd-level Cache Read Misses is measured on the Bus and counts memory load misses and read-for-ownership misses. Look like it counts the instruction misses as well.
If the L2 is the last level cache in the system (which is the case for Xeon Nocona), the L2 cache misses penalty can be calculated as L2 Cache Read Misses * 150 clocks penalty (rough estimation)