Hi,
I am trying to understand the behavior the precise MEM_LOAD_RETIRED events on the Nehalem architecutre.In Dr. Levinthal's Performance Analysis Guide for Core i7 processors, he says "The sum of all the MEM_LOAD_RETIRED events will equal the MEM_INST_RETIRED.LOADS count", but I am unclear whether this should include theMEM_LOAD_RETIRED.DTLB_MISS. In particular does a memory load that misses the LLC and the DTLB trigger both the LLC_MISS and DTLB_MISS events or are they mutually exclusive?
Collecting these events using VTune 9.1, I get the following event counts:
MEM_LOAD_RETIRED.L1D_HIT: 1.14012919578e+12
MEM_LOAD_RETIRED.L2_HIT: 19825622442.0
MEM_LOAD_RETIRED.LLC_UNSHARED_HIT: 4728934890.0
MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM: 671512.0
MEM_LOAD_RETIRED.LLC_MISS: 13631235388.0
MEM_LOAD_RETIRED.HIT_LFB: 29051985285.0
MEM_LOAD_RETIRED.DTLB_MISS: 24331796790.0
I am surprised to see that the number DTLB_MISS events is almost twice as large as the number of LLC_MISS events. I understand that there may be edge cases in which we see a DTLB miss and a LLC hit (e.g. as disscussed at
http://origin-software.intel.com/en-us/forums/showthread.php?t=70535), but I would expect these to be relatively infrequent.
Am I misinterpreting these counters? I'm really just trying to find the fraction of loads serviced by each level of the memory hierarchy, and I'm not sure what to do with the DTLB misses.
Thanks,
Ben
