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SB_DRAIN.ANY and RESOURCE_STALLS.STORE

Tushar_S_
Beginner
188 Views

hi all

I have difficulty in understanding westmere pmc counters SB_DRAIN.ANY and RESOURCE_STALLS.STORE

Could you please let me know what exactly these counters do?

thanks

-ts

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1 Solution
TimP
Black Belt
188 Views

The posted definitions seem clearer than many.

On the assumption that the store buffer events relate to the fill buffers, did you consult

https://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf ?

Do you also see significant counts on one of those fill buffer events?

A typical situation might be that the code is updating more than 10 cache lines in a loop, so that partially updated cache lines have to be flushed and replaced with contents of the next cache line to be updated.

As the resource stall definition specifically calls out 5 possibilities (each of which has its own specific counter, including a store buffer event), I doubt anyone could tell at a distance which of those it might be.  They seem to have in common that they are pipeline stalls or stalls on instructions which specifically require waiting for the pipeline to clear.

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1 Reply
TimP
Black Belt
189 Views

The posted definitions seem clearer than many.

On the assumption that the store buffer events relate to the fill buffers, did you consult

https://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf ?

Do you also see significant counts on one of those fill buffer events?

A typical situation might be that the code is updating more than 10 cache lines in a loop, so that partially updated cache lines have to be flushed and replaced with contents of the next cache line to be updated.

As the resource stall definition specifically calls out 5 possibilities (each of which has its own specific counter, including a store buffer event), I doubt anyone could tell at a distance which of those it might be.  They seem to have in common that they are pipeline stalls or stalls on instructions which specifically require waiting for the pipeline to clear.

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