Virtual IO Pin mapping introduces negative setup setup slack

[sgannava]

Hi All,

I have a Quartus Prime Standard reference design working as expected with positive setup slack and I can achieve the frequency of 470MHz.

Now that I am using Virtual IO Pin mapping for all the pins (by using corresponding tcl commands during syntesis stage) in my design and this introduces a negative setup slack in my design.

As per my understanding, setup slack (S) = Required time (R) - Arriavl Time (A)

S = R - A

where this R depends on my target frequency(I mean the clock period)

So, I tried to fix it by lowering the frequency from 470MHz as it can make the setup slack turn positive. But, I can see the setup slack is going more negative by lowering the frequency.  To the surprise, increasing the frequency to 480MHz (not beyond 500MHz), makes the setup slack positive.

FYI, I have initially used quartus_sta executbale for synthesis. Now, after including virtual IO mapping tcl command, I had to use quartus_sh executable

Can someone guide me in understanding?

1. Why virtual IO pin mapping is introducing the negative setup slack?

2. Why the setup slack is  turning positive with increase in frequency?

3. Does change in the executable at Synthesis stage is causing any issue?

I have also attached the tcl scripts as a ZIP file I am using for synthesis(quartus_sh executable is used), planning(quartus_sta), place&route(quartus_sta)

Thanks

Sai G