This group contains events that monitor various stall conditions.
Delayed bypass to FP operation.
Delayed bypass to load operation.
Delayed bypass to SIMD operation.
Loads blocked by the L1 data cache.
Loads that partially overlap an earlier store, or 4K aliased with a previous store.
Loads blocked by a preceding store with unknown address.
Loads blocked by a preceding store with unknown data.
Loads blocked until retirement.
Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction.
Self-Modifying Code detected.
Retired loads that miss the DTLB (precise event).
L1 data cache line missed by retired loads (precise event).
Retired loads that miss the L1 data cache (precise event).
L2 cache line missed by retired loads (precise event).
Retired loads that miss the L2 cache (precise event).
All RAT stall cycles.
Flag stall cycles.
Flag stall events.
FPU status word stall.
Partial register stall events.
Partial register stall cycles.
ROB read port stalls cycles.
Resource related stalls.
Cycles stalled due to branch misprediction.
Cycles stalled due to FPU control word write.
Cycles during which the pipeline has exceeded load or store limit or waiting to commit all stores.
Cycles during which the ROB is full.
Cycles during which the RS is full.
Cycles while stores are blocked due to store buffer drain.
Cycles while store is waiting for a preceding store to be globally observed.
A store is blocked due to a conflict with an external or internal snoop.
RESOURCE_STALLS.ANY 239050 215770
RESOURCE_STALLS.LD_ST 71716 141970
RESOURCE_STALLS.RS_FULL 16638 76847
Rest is quite similar in both.What could that mean?