I want to know how to test my code with VTune
and what the event is equivalent to
number of L1 cache miss
cost of a L1 cache miss
number of L2 cache miss
cost of an L2 cache miss
number of write access
Cost of a write access
number of read access
out a read access
Thank you for the link
I ask you if you have another link
I want to know if VTune allows me to have a curve that shows the change of program in abcsisse the data size and in cordones the cost formula is entered (eg the number of L2 cache miss)
Thank you very match
I want to know the number of access in reading and writing and their cost of my program with VTune is that it is possible and what are these events because I have not found
Thank you very much
I dont know why you need to calculate the cost of all readings and writings for the program. General methodology is to estimate the program performance and to find out the hotspots (using the default sampling configuration). Once youve identified the hotspots, you can configure the sampling activity by adding countable eventsto identify the performance issues and estimate their cost using the data provided in the white paper. Appropriate events are listed there as well.
I need access costs in reading and writing as well as the number of L1 cache miss and L2 and their costs is by my program to calculate the total time of my program based on a model that is an equation based on these terms
I want to know if VTune gives me thes values or it is the analysis and the indication of hotspots only
the model or the equation that I am trying to find its corresponding values depends on some values estimated by VTune
in fact I need the number and cost of access to L1 cache, L2, writing and reading only in my model
it is a simple equation that does not depend on several parameters to calculate the end time total progrmme
MEM_LOAD_RETIRED.L1D_LINE_MISS gives me the number of L1 cache miss my program?? Or the number of L1 miss doing my programs depends on several other event?
As I said earlier, it's complicated. MEM_LOAD_RETIRED.L1D_LINE_MISS does NOT give the number of L1 cache misses in your program. Here is the description of this Intel Core i7 event:
This event counts the number of load operations that miss the L1 data cache and send a request to the L2 cache to fetch the missing cache line. That is the missing cache line fetching has not yet started. This event count is equal to the number of cache lines fetched from the L2 cache by retired loads. The event might not be counted if the load is blocked (see LOAD_BLOCK events).
So to start, it's not counting "cache misses" but "cache line misses" and not all of them. There are L1 data cache misses that are not being counted here (if they are to an L1 cache line that's already been missed--there's a separate event to count all those) and there are various load blocking conditions (which are also described in the VTune reference manual) that keep this event from being counted.
Also consider this: MEM_LOAD_RETIRED.L1D_LINE_MISS tells you the number of cache line requests that went from L1 data to L2; it doesn't tell you how many of those events were for cache lines that were already in L2 versus those that required a subsequent last level cache request or ultimately amemory fetch to satisfy an L2 miss. So I end as I started, by saying that these mechanisms are complicated and formulaic approaches to prediction are likely to be frustrated by the stochastic nature of the machine internals.