AN 754: MIPI D-PHY Solution with Cyclone V - questions on VCCIO/VCCDP/VREF connection

[DdRd]

I am referring to the AN 754 (MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs) to acheive MIPI receive in Cyclone IV.

We can see in the document at Table 1, in FPGA I/O buffer mode for RX, that :

- For high-speed signaling mode, we can use differential I/O standard (LVDS25) 

- For low-power signaling mode, we can use single-ended mode with HSTL12 or LVCMOS12 I/O standard 

I would like your approval, for FPGA I/O buffer in RX mode only and for low-power signaling only, that we can use HSTL12 single-ended mode with the following connections for the same IO bank:

1) VCCIO=2.5V

2) VCCPD=2.5V

3) VREF=0.6V

4) and that there is no need for any VTT connection at all

I will be grateful if there is someone that can give me an approval on the connections detailed in items 1/2/3/4.

Thanks in advance.

[DdRd]

I will appreciate a lot if you can update me that anyone is working on my question...

[AqidAyman_Intel]

Hello,

You wanted to connect HSTL-12 with the 1/2/3/4 requirement.

May I reconfirm with you with my understanding?

Regards,

Aqid

[DdRd]

Hi Aqid,
Yes, I confirm but HSTL-12 is in RX mode only.
Thanks.
Regards,
David R.

[AqidAyman_Intel]

Hello David,

Referring to Cyclone IV datasheet for HSTL-12 I/O standard, I afraid some of the requirements are not meeting the specification.

HSTL-12 need a typical 1.2V VCCIO and need VTT. Refer here:

https://www.intel.com/content/www/us/en/content-details/653974/cyclone-iv-device-handbook.html?wapkw=cyclone%20iv%20datasheet

Regards,

Aqid

[DdRd]

 Hi Aqid,

I would like you to double check because of the followings:

A) Per Intel document AN 754 (MIPI D-PHY Solution with Cyclone V), at Figure 3, there is no need for VTT.

B) Per same document AN 754, at Table 1, for FPGA I/O RX mode , for Low-power signaling mode and for HTSL-12 I/O standard, I/O voltage Supply is defined as 2.5V.

More than this, there is two notes (1) + (2) in the same table:

(1) The LVDS can co-exist in the same I/O bank as HSTL-12 when the FPGA is configured as input buffer in Cyclone® V devices.

(2) Input buffer for LVDS and HSTL-12 I/O standards are powered by VCCPD in Cyclone® V devices.

C) Also per Intel document CV-5V2 (Cyclone 5 Device Handbook), at Table 5-9, we can see that for 1.2V HSTL, VCCIO needed for input is VCCPD when VCCPD=2.5V

More than this, there is a note (11) in the same table:

(11) Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,
HSUL, and Differential HSUL are powered by VCCPD

Thanks in advance.

Regards,
David R.

[AqidAyman_Intel]

Hello David,

Are you referring to Cyclone IV or Cyclone V? In your early description it mentioned on Cyclone IV. I really apologies if I understand it wrongly.

As if for Cyclone V, as your findings and pointing out the document, it should be okay to connect with the requirement in 1/2/3.

However, for the VTT, based on the CV-5V2 (Cyclone 5 Device Handbook), at Table 5-9, it should have connection to VTT=0.6V.

As for the Figure 3 you showed in AN754, it mentioned Cyclone IV.

[DdRd · Accepted solution]

Hi Aqid,

The AN754 refers to the Cyclone® IV, Cyclone V, Intel® Cyclone 10 LP, Intel MAX® 10.

But sorry for the typo, I am referring specicially to the Cyclone V.

Thanks for the approval, so it should be okay to connect with the requirement in 1/2/3:

1) VCCIO=2.5V

2) VCCPD=2.5V

3) VREF=0.6V

Regarding the VTT, I will follow the AN754 at Figure 1 (FPGA Unidirectional Receiver Implementation Block Diagram) or at Figure 3 (FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit) that is not using VTT at all.

THANKS A LOT FOR THE SUPPORT - I appreaciate a lot!!!

Regards,
David R.

[AqidAyman_Intel]

Hello David,

Thanks for the clarification.

I am happy to help you!

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