Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
477 Discussions

Cyclone V Errata: False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode

rfern33
Beginner
853 Views

Hi,

 

I have a few 5CEFA2F23C8s some of which require me to perform the "False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode" workaround as per "Cyclone V GX, GT, and E Device Errata" while some of the FPGAs do not. It is possible the ones that do not require this are from an older batch.

 

I would like to know why some of the FPGAs require us to perform this workflow. Is there a batch(es) that we could buy to avoid us from having to do this workaround?

 

See the attached screenshot for the workaround. Link to the errata can be found below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es_cyclone_v.pdf

 

Support Ticket - 04464979

0 Kudos
5 Replies
YuanLi_S_Intel
Employee
671 Views

Hi Reuben,

 

This is only happening when the FPGA is using AS x1 Mode. Apologize that all the batches are affected by this. Thus there is no way to avoid from this.

 

Thank You.

 

0 Kudos
rfern33
Beginner
671 Views

Thanks for the response @SooY_Intel​ .

 

 

Out of curiosity, is there a way to run a CRC to ensure the FPGA was successfully programmed? I think this is described in Section 8.2 and 8.3 of the Cyclone V Device Handbook.

https://www.intel.com/content/www/us/en/programmable/documentation/sam1403481100977.html#sam1403479152636

 

I am simply looking for a way to guarantee:

  • Deployment to the EPCQ16A IC was successful
  • Cyclone V was programmed correctly

 

Reuben

 

0 Kudos
YuanLi_S_Intel
Employee
671 Views

I dont understand. The CRC will be implemented by default during device programming. Thus, we no need to run that. It will be ran by default.

0 Kudos
rfern33
Beginner
671 Views

Right. Do you know if this CRC is performed when we program the Configuration IC (EPCQ16A) or when the FPGA enters User Mode?

 

I am trying to ensure that disabling the CONF_DONE error checking flag does not compromise any security measures.

 

0 Kudos
YuanLi_S_Intel
Employee
671 Views

No sir, this CRC runs during configuration phase only. It is not advised to diable the CONF_DONE flag as it is needed during configuration.

0 Kudos
Reply