Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
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HLS and Time-Division Multiplexing

ArthurDent
New Contributor I
1,331 Views

Hi

E.g. when designing a filter using the "FIR II IP Core" you specify both the input sample rate and the clock speed: When the clock rate is far larger than the sample rate the filter generated uses very few DSPs and logic resources.

Is it possible to do the same with HLS?

Will HLS get Time-Division Multiplexing support?

BR

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1 Solution
MuhammadAr_U_Intel
658 Views
Hi, HLS has always supported resource sharing like what you are asking for, but you would need to code the behavior. Resource sharing is generally achieved by putting the hardware you would like to share in a loop or a task (See Systems of Tasks documentation and tutorials available in 19.1). - /examples/tutorials/best_practices/resource_sharing_filter/ - /examples/tutorials/system_of_tasks/resource_sharing/ Thanks, Arslan

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MuhammadAr_U_Intel
659 Views
Hi, HLS has always supported resource sharing like what you are asking for, but you would need to code the behavior. Resource sharing is generally achieved by putting the hardware you would like to share in a loop or a task (See Systems of Tasks documentation and tutorials available in 19.1). - /examples/tutorials/best_practices/resource_sharing_filter/ - /examples/tutorials/system_of_tasks/resource_sharing/ Thanks, Arslan
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