How can I use my transitional windows based FPGA design flow experience into OPAE design flow

[User1582192733150209]

Hello Sir/Madam,

For Intel PAC arria10gx hardware platform, the suggested development ​flow is to follow OPAE design guideline,which ask user to follow CCIP protocol and is a terminal based synthesis and placing and routing flow.

I am analyzing the example of hello_AFU and nlb_mode_0_stp, all these design can be synthesis and to generate image file.which is good.

My question is

1,During the processing I can open the QUARTUS prime GUI with opening the dcp.qsf, Does this project include AFU and FME,FIU,FME all modules?because I can't find these static module from logiclock window and design partition window. In the traditional partial reconfigration design flow ,we can see all design partitions in above 2 windows.

2,Can I do syntheses and place and routing in GUI ? I found quartus GUI report error if I do place and routing. because once GUI lunched, click start is always easier than tcl command.

3, Can intel PAC card support traditional design flow if I do not need CPU do anything for time being? If so , any resource I can have? I found there is no schematic and FPGA Pinout document at all from website, where can I get these document?

thanks

Jim

[JohnT_Intel]

Hi,

1,During the processing I can open the QUARTUS prime GUI with opening the dcp.qsf, Does this project include AFU and FME,FIU,FME all modules?because I can't find these static module from logiclock window and design partition window. In the traditional partial reconfigration design flow ,we can see all design partitions in above 2 windows.

Unfortunately no. You are not able to view it as the static region design has been encrypted.

2,Can I do syntheses and place and routing in GUI ? I found quartus GUI report error if I do place and routing. because once GUI lunched, click start is always easier than tcl command.

No. It is recommended to use command mode to compile it as it need to run its own flow.

3, Can intel PAC card support traditional design flow if I do not need CPU do anything for time being? If so , any resource I can have? I found there is no schematic and FPGA Pinout document at all from website, where can I get these document?

No., it is not supported.

[User1582192733150209]

Thansk, JohnT, your feedback is very useful.

have a good day

jim

[JohnT_Intel]

Your welcome. Feel free to submit new issue into the forum.

Have a good day.