I want to create one FPGA version (one gbs file) that will consist of my RTL files and an OpenCL file that will accelerate into the FPGA (by OpenCL Kernel compiler).
How can i do it?
An OpenCL kernel compiled with the OpenCL compiler will directly connect to the interfaces defined in the OpenCL BSP. If your RTL needs access to FPGA I/O, then you should add that to the OpenCL BSP and recreate the BSP, which will be a difficult task. If, however, your RTL does not need to access FPGA I/O, you can convert it to an RTL library as describe in Intel FPGA SDK for OpenCL's guides, and then directly instantiate that library in an OpenCL kernel. The last option is to convert your OpenCL kernel to an HLS kernel and compile it using Intel's HLS compiler into an HDL module and then integrate it with your existing RTL module and other necessary IP cores through Qsys.
First of all, thank you!
I need connect my RTL to IO. I need to connect it to a 10G MAC.
Also I need DDR too.
Do you know a guide that explains how to do this?
Maybe reverse? Maybe there is a way to insert the OpenCL compiler result into the AFU environment that I created as a FPGA developer.
You cannot connect an OpenCL kernel to an HDL module that needs I/O access since an OpenCL kernel has to be compiled against, and will automatically connect to, the interfaces provided by an existing BSP, and only the BSP can access I/O. You can, however, add your HDL module and associated I/O access to the BSP, and maybe even provide I/O channels to access said I/O inside of the OpenCL kernel. Follow the link provided by @KennyT_Intel for instructions as to how you can create/modify an OpenCL BSP. Your other option, as I mentioned earlier, is to convert your OpenCL kernel to an HLS kernel and compile it to an HDL module with your own chosen interfaces using the HLS compiler and then connect the generated HDL module to your existing HDL and interfaces. You can find the documents for the HLS compiler here: