Hi,
I using the card intel PAC arria 10 gx FPGA(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/intel-pac-with-arria-10-gx-product-brief.pdf).
My goal is to create an FPGA accelerator that uses the DMA for the
transaction of data between host and local memory of the FPGA. To do
this, I use the example "dma_afu" present on the Github (OPAE)
website. I want to insert a processing module inside the example.
I guess to add a module inside the "msgdma_bbb" block in this manner:
the processing module is put between "the dma_read_master" and
"dma_write_master", and connected to them through the avalon_st interface.
This additional module must include an enabling signal which, if it is
off, will not make any changes to the data (normal operation) and if it
is on, the data will be processed.
My problem is that I can't find a signal that can be used for this purpose.
I was suggested to use the csr_slave signal used in the dispatcher but I
do not know to do this. Any suggestion?
Thanks.
Best regard
