In Q18.1 and A10 FPGA，Whether can I capture the PERST de-assertion and image loading complete in the signaltap？

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In Q18.1 and A10 FPGA，Whether can I capture the PERST de-assertion and image loading complete in the signaltap？

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Yes, you could capture the PERST de-assertion using signaltap for Arria 10 FPGA.

Regards,

Nathan

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