Community
cancel
Showing results for 
Search instead for 
Did you mean: 
ADua0
Beginner
828 Views

Intel Opencl FPGA channels

I have a Opencl design which requires use of Intel opencl Fpga channels for communication between two kernels. I need to know what factors should decide about the channel depth ?

0 Kudos
7 Replies
HRZ
Valued Contributor II
182 Views

The main factor would be the amount of mismatch in the rate of writing into the channel and reading from it. If these rates are expected to be similar in both of your kernels, then a shallow depth of a few indexes (<20) will suffice and will not use Block RAMs either. If, however, the rate is expected to be very different, then you should keep increasing the depth and measure the performance to see when the performance will become stable.

ADua0
Beginner
182 Views

Thanks for the reply. @HRZ​ . Does this also hold for both the cases when stall is at reading and writing side? what I think is having stall at write side means , channel depth could help but not for reading side ?

HRZ
Valued Contributor II
182 Views

When you have a similar amount of stalling on both the read and the write side, it means the source of stall is not the channel but something else. Indeed increasing channel depth will not help if you only have stalls on the read side but not on the write side.

ADua0
Beginner
182 Views

Just another follow up question @HRZ​ , I have a stall on write side( no reading from memory, just sending constant values) , but what I initially thought of increasing depth did not help, could there be any other possible reason for that ?

HRZ
Valued Contributor II
182 Views

I have no idea. You can check "Section 4.3. Interpreting the Profiling Information" from Best Practices Guide which has extensive information describing how to interpret profiling results and finding sources of bottleneck.

ADua0
Beginner
182 Views

Thanks , I will take a look into it

DongWang-BJTU
New Contributor I
182 Views

The compiler will change the depth during compilation, maybe that why the behavior is not what you have expected.

Reply