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Linking top level RTL function with all its required modules using the OpenCL RTL library workflow


I have a top level verilog function, within it I instance some other modules. I have written the xml file and c_model as well as calling the top level verilog function in my OpenCL kernel (following the steps in example 1 and 2 as given by Intel for the OpenCL library: Currently all the other modules are as separate verilog files in the same directory as my top level function.


My question is how do I link all the other modules the top level function is going to use. I looked at the design examples Intel have provided but couldn't find the answer.



(NOTE: I am not intending to access external memory like in example 2 that Intel provides - view link)


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If you look into the example 2 <directory>\library_example2\device, you see the This is the top level files that you can follow. You can look inside the lib files how they link btw *.cl and *.v code.
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