Application Acceleration With FPGAs
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No able to run Intel FPGA AI Suite Soc Design Example User Guide example on Intel Arria 10

RubenPadial
New Contributor I
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Hello,

I have an Intel Arria 10 SX SoC FPGA Development Kit and I'm starting with the Intel FPGA AI suite. I was trying to run  Intel FPGA AI Suite Soc Design Example User Guide example, but I'm not able.

 

  1. If I try to build FPGA bitstream according to 3.3.2 section, I get a license error. I got to another forum thread and it suggests that host pc memory could be full but while this process is running I got 8 or 9 GB over 128GB RAM memory. What could be the problem? You can find attached 'build.log' file
  2. When I use the precopiled image with the precompiled bitstream, I'm not able to run the resnet-50-tf examples as per section 3.7.1. I compiled the graphs using A10_Performance.arch architecture file according to 3.6.3 section. However, when I run the application on Intel Arria board I an error related to the architecture file.

"Arch check failed:compiledResult arch hash is db8c5e25 cb7fd99d 00000000 00000000 , bitstream arch_hash is d1eb0625 6ebbf77a 00000000 00000000
This check can be disabled by setting environment variable DLA_DISABLE_ARCH_CHECK=1."

It seems that bitstream was not compiled with the same architecture file I compiled the graphs. I tried with others example architecture files available in 'example_architectures' folder with the same result.

In addition setting DLA_DISABLE_ARCH_CHECK=1 I get another error:

"

[ ERROR ] Infer failed

[Step 11/12] Dumping statistics report
count: 4 iterations
system duration: 30022.6073 ms
IP duration: 30442.5643 ms
latency: 30022.4879 ms
system throughput: 0.1332 FPS
number of hardware instances: 1
number of network instances: 1
IP throughput per instance: 0.1314 FPS
IP throughput per fmax per instance: 0.0007 FPS/MHz
IP clock frequency: 200.0000 MHz
estimated IP throughput per instance: 102.3036 FPS (265 MHz assumed)
estimated IP throughput per fmax per instance: 0.3861 FPS/MHz
[Step 12/12] Dumping the output values
[ INFO ] Comparing ground truth file /home/root/resnet-50-tf/sample_images/TF_ground_truth.txt with network Graph_0
top1 accuracy: 0 %
top5 accuracy: 0 %
[ INFO ] Get top results for "Graph_0" graph passed
WaitForDla interrupt timeout with threadId_1
If inference on one batch is expected to take more than 30 seconds, then increase WAIT_FOR_DLA_TIMEOUT in dlia_plugin.cpp and recompile the runtime.
WaitForDla interrupt timeout with threadId_2
If inference on one batch is expected to take more than 30 seconds, then increase WAIT_FOR_DLA_TIMEOUT in dlia_plugin.cpp and recompile the runtime.
WaitForDla interrupt timeout with threadId_3
If inference on one batch is expected to take more than 30 seconds, then increase WAIT_FOR_DLA_TIMEOUT in dlia_plugin.cpp and recompile the runtime."

 

I'm only following the Intel FPGA AI Suite Soc Design Example User Guide, and I cannot make the example work on my development board. Is it for this board? How I can manage to run the example?

Thank you in advance

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12 Replies
JohnT_Intel
Employee
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Hi,


In order to re-compile the design, you will need to purchase AI Suite IP licence. You will need to contact your local sales to get the pricing for the IP.


For using the precompiled bitstream, may I know which version of AI Suite version are you using? What is the bitstream name are you using?


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RubenPadial
New Contributor I
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Hello @JohnT_Intel 

I'm using the Intel FPGA AI suite 2023.1 with OpenVino Toolkit 2021.4.2 as required, running on a Ubuntu 20.04 host computer.

The precompiled I'm trying to use is the one is given in the sesction "3.4. Writing the SD Card Image ( .wic ) to an SD Card" of the Intel FPGA AI Suite Soc Design Example User Guide "$COREDLA_ROOT/demo/ed4/a10_soc_s2m/sd-card/coredla-image-arria10.wic"

 

Thank you for your help

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JohnT_Intel
Employee
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Hi,


Thanks for the clarification.


Are you trunning the design based on the S2M or S2M? Can you provide me the you used and also the log file?



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RubenPadial
New Contributor I
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Hello @JohnT_Intel 

I tried to run both the S2M and the M2M examples. You can download them in the following link: Intel_FPGA_AI_Suite_SoC_Design_Example.zip.

Let me know if you need any other file.

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JohnT_Intel
Employee
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Hi,


I observed that you have the xml and bin file needed to run the demonstration. Since you are using the pre-comile .wic file, you may directly skipped to Chapter 8 S2M Streaming Demonstration.


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RubenPadial
New Contributor I
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Hello  @JohnT_Intel 

In section 3.4 is specified that either the precompiled .wic image or the built by my own image can be loaded to the SD card without any difference. In addition, there is no information about skipping to the Chapter 8 in all the chapter 3, so I understand all steps are compatibles, except for the building or not the bitstream.

In addition, In section 4.2 is mentioned that every graph for the demostration SD card must be compiled using A10_Performance.arch file as I did.

According to section 8.4.1. The streaming_inference_app Application built files must be copied to /home/root/resnet-50-tf in order to run S2M example. resnet-50-tf directory does not exist in the precompiled SD image, so I created it and copied "RN50_Performance_no_folding.bin" and "A10_Performance.arch" files into this folder. That is what I was doing before and I got the error message when I run "streaming_inference_app". So, as far this chapter is concerned, it's needed to compile .bin file (graph) from the .xlm file, isn't it?

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JohnT_Intel
Employee
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Hi,


You willl need to followw Chapter 4.1 which will refer you to follow "Intel FPGA AI Suite Getting Started Guide" section 6.2 on howw to generate the .bin/.xml files for ResNet50 in order to run the appllication.


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RubenPadial
New Contributor I
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Hello @JohnT_Intel 

In the section 4.1 there's no reference to "Intel FPGA AI Suite Getting Started Guide". I followed 3.6.3. Compiling the Graphs from the same document and, indeed, I used A10_Performance.arch file to compile graph:

"

cd $COREDLA_WORK/demo/models/public/resnet-50-tf/FP32
dla_compiler \
--march $COREDLA_ROOT/example_architectures/A10_Performance.arch \
--network-file ./resnet-50-tf.xml \
--foutput-format=open_vino_hetero \
--o $COREDLA_WORK/demo/RN50_Performance_no_folding.bin \
--batch-size=1 \--fanalyze-performance \
--ffolding-option=0

"

However It doesn't work. Which architecture file is needed to compile the graphs? Is "A10_Performance.arch" the correct one? Why checksum check fails then?

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JohnT_Intel
Employee
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Hi,


The flow to generate the graph is correct. Can you try running the flow below.


In the first terminal:

cd /home/root/app

./run_inference_stream.sh


In the second termnial:

cd /home/root/app

./run_image_stream.sh


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RubenPadial
New Contributor I
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Hello @JohnT_Intel ,

That's what I'm exactly doing but no sooner did I run ./run_inference_stream.sh than it prompted me the architecture mistmach error message.

Was the prebuilt SD image built with the same architecture file I'm using?

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RubenPadial
New Contributor I
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Hello @JohnT_Intel ,

 

I updated to Intel FPGA AI Suite 2023.2. I followed the Intel FPGA AI Suite Soc Design Example User Guide for this version and the example is running. I have noticed that resnet-50-tf.xml and coredla-image-arria10.wic files have changed. However, A10_Performance.arch remains the same. Could you confirm the architecture file used to build coredla-image-arria10.wic was exactly the same in both versions or coredla-image-arria10.wic file was built with other architecture file?

Thank you in advance.

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JohnT_Intel
Employee
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Hi,


The wic file will be different. Since you are able to run using the latest release AI Suite then please use this version.


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