Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, DLA, Software Stack, and Reference Designs
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
426 Discussions

Power Monitoring tool - Arria 10 GX board

mvemp
Novice
1,792 Views

I am trying to measure power using the Power monitoring tool. I obtain a static power of 14W. When my FPGA is being programmed I see a drop in power consumption (9W). When I run the application, i dont see any changes. Its still 14W. I use FPGA OpenCL SDK to launch my applications.

 

Anyone uses OpenCL SDK and power monitoring tool? The latency of my application is less than 10ms.

 

I have attached screenshot of my power results as reference.

 

0 Kudos
1 Solution
AnandRaj_S_Intel
Employee
502 Views

Hi,

 

If the graph is referring to Power it doesn’t make sense. I expect Power to spike during configuration, and drops back down in user mode.

If it is referring to Voltage, it makes total sense. I expect voltage to take a dip during configuration, (depends on regulator feedback response) it will correct it back to the stable 0.9VCC.

 

I would suggest a sanity check.

1)     Scope on the VCC line and see if waveform match the powermonitoring waveform during configuration.

2)     Run an EMIF design. It should consume lots of power. I don’t think running a counter + LED will show any significant change in power. Then monitor your waveform and see if match with the powermonitoring.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

 

View solution in original post

1 Reply
AnandRaj_S_Intel
Employee
503 Views

Hi,

 

If the graph is referring to Power it doesn’t make sense. I expect Power to spike during configuration, and drops back down in user mode.

If it is referring to Voltage, it makes total sense. I expect voltage to take a dip during configuration, (depends on regulator feedback response) it will correct it back to the stable 0.9VCC.

 

I would suggest a sanity check.

1)     Scope on the VCC line and see if waveform match the powermonitoring waveform during configuration.

2)     Run an EMIF design. It should consume lots of power. I don’t think running a counter + LED will show any significant change in power. Then monitor your waveform and see if match with the powermonitoring.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

 

Reply