Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
477 Discussions

Stuck with alt_sld_fab file related error while generating GBS file for AFU

UTech
Beginner
815 Views

Hi,

 

I have created an AFU setup integrated with CCIP, Memory(DDR) and MAC. Currently I'm stuck at synthesis phase of GBS file generation(I'm adding .qip and .ip files in filelist.txt).

 

I''m seeing partition failure which is breaking the GBS generation, and even before the tool throws partition failure, I'm seeing an error where certain file named "alt_sld_fab_0" was not found.

 

Based on some online suggestions, I removed stp related files(directed to e10 folder, ethernet folder) from Quartus>Project>Add/remove files form Project. But it didn't help. Please note signal tap analysis is disabled in properties.

 

I'm attaching the file with detailed error report, please find it in attachments.

 

Technical Details:

Software : Intel Quartus Prime Pro 17.1.1

Target Card : Intel Programmable acceleration card with Intel Arria X FPGA

 

Any suggestion on this will be helpful.

 

Thank you.

0 Kudos
9 Replies
JohnT_Intel
Employee
595 Views

Hi,

 

May I know which DCP version are you using? Have you tried to compile using the simple design that is part of the DCP package?

0 Kudos
UTech
Beginner
595 Views

Hi,

 

Hope by mean you mean acceleration stack version. Our acceleration stack version is 1.1

 

We got the .gbs file generated for hello_afu example provided by Intel.

0 Kudos
JohnT_Intel
Employee
595 Views

Hi,

 

Is it okay for you to update to acceleration stack version 1.2?

0 Kudos
UTech
Beginner
595 Views

Hi,

 

Can you give some more details on the error and how it will be resolved by 1.2? Because we were advised by the Intel team that the Arria10 PAC card which is available with them supports only 1.1

 

0 Kudos
JohnT_Intel
Employee
595 Views

Hi,

 

The package is verified to be able to compiled. Could you provide me the step you used to compile the design?

0 Kudos
UTech
Beginner
595 Views

Hi,

 

Step - 1 : afu_synth_setup --source hw/rtl/filelist.txt build_synth

Step -2 : cd build_synth

Step -3 : $OPAE_PLATFORM_ROOT/bin/run.sh

0 Kudos
JohnT_Intel
Employee
595 Views

Hi,

 

Could you try to compile using Acceleration Stack 1.2? You should be able to upgrade your board with this version as well.

0 Kudos
UTech
Beginner
595 Views

Hi,

 

Sure, I will try with Acceleration Stack 1.2

0 Kudos
JohnT_Intel
Employee
595 Views

Hi,

 

Please let me know if you face any issue compiling the AFU on Acceleration Stack 1.2.

0 Kudos
Reply