TRANSCEIVER REFERENCE CLOCK INPUT IN CYCLONE V

[mhm00]

Hi,

I'm using Cyclone V GX 5CGXFC5C6F23I7N FPGA.

1) For 3.125Gbps data rate what could be the Frequency for REFCLK input in Transceiver section.

2) Which IO standard should i use for REFCLK.

3)What could be the termination for REFCLK.

4)I'm using VCCH_GXBL=2.5V, VCCL_GXBL=1.1V and VCCE_GXBL=1.1V so what could be the supply voltage for external OSCILLATOR.

5)is COUPLING needed or not? If yes what type of coupling (AC or DC)needed,how to do that.

[mhm00]

HI,

I found the solution for Question No.3. answer was in the cyclone v datasheet Transceiver Performance Specifications.

Termination for Refclk is 100 ohm,and it is On chip termination.

for detail information go through the attached file.

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to CV XCVR. Please see my responses as following:

1) For 3.125Gbps data rate what could be the Frequency for REFCLK input in Transceiver section.

[CP] Generally each data rate will have a few support refclk frequencies. You may check the supported frequencies in Native PHY by configuring to your target data rate and then look at the drop down list of the refclk.

2) Which IO standard should i use for REFCLK.

[CP] You may refer to the "Reference Clock Specifications for GX, GT, SX, and ST Devices" table in the CV datasheet for the supported IO standards ie 1.5V PCML, LVDS and etc.

3)What could be the termination for REFCLK.

[CP] I believe you have found the specific specs from the datasheet.

4)I'm using VCCH_GXBL=2.5V, VCCL_GXBL=1.1V and VCCE_GXBL=1.1V so what could be the supply voltage for external OSCILLATOR.

[CP] For your information, you would need to refer to the oscillator datasheet on the supply voltage to be used. For the interfacing with CV XCVR refclk, you would need to ensure the output of oscillators meet the refclk specs as in the "Reference Clock Specifications for GX, GT, SX, and ST Devices" table of CV datasheet.

5)is COUPLING needed or not? If yes what type of coupling (AC or DC)needed,how to do that.

[CP] For refclk, apart from HCSL IO standard for PCIe application, AC coupling is required. You might need to further discuss with your board design on the AC coupling implementation as it is part of board design and something not controllable by FPGA. Hope you could understand it.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin