Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
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Total register & logic consumed from Arria 10 PAC

E-Hong
New Contributor I
‎06-07-2021 09:22 PM
920 Views

Hi,

 

Is there any ways to obtain the amount of register and logic consumed from running inference on the Arria 10 PAC? I am trying to get the sof/pof report like those generated on Quartus when running synthesis.

 

Does programming a bitstream on the Arria 10 PAC generate a report?

 

Thank you.

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EricMunYew_C_Intel
Moderator
‎07-06-2021 03:04 AM
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You can find the details from the following:

/build_synth/build/output_files/afu_default.fit.rpt


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E-Hong
New Contributor I
‎07-24-2021 12:11 AM
838 Views
In response to EricMunYew_C_Intel

Hi,

Can I perform this on DevCloud Edge as well? If so, what is the path to the rpt file?

 

Thank you.

In response to EricMunYew_C_Intel
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