One of my project, i am using Cyclone 10LP, due to obsolete of cyclone first gen, i am using 10LP for reading frequency,
Problem is : I am not able to read frequency when IO is connected to proven circuit (comparator opamp, working with OLD cyclone first generation PCB), same i can able to read when i connect Signal generator.
later i found that this is because of input signal is ON when i powered on PCB/FPGA,
if signal generator(input signal) is on and power on PCB, doesn't read frequency.
first power on PCB then power on input signal this will read input signal fine.
Can we add power-on delay in FPGA block diagram,
i am new to FPGA block diagram coding. need support for this.
Apologize that we cannot do power-on delay in FPGA. Perhaps that need to be done on board level.
In Board level their is a 5 to 7 Sec input power-on Delay,
Is this timing is sufficient to configure from EEPROM(EPCQ4ASI8N)?
is their any option to figure out the timing required/reduce the time for FPGA ready? and start the reading the input.
may i know what is the configuration you use? If you are using active serial configuration, delay doesn't affect it as the FPGA will get the bitstream from flash and do the programming.